board/freescale/ls1043ardb/ddr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __DDR_H__
   7 #define __DDR_H__
   8
   9 extern void erratum_a008850_post(void);
  10
  11 struct board_specific_parameters {
  12         u32 n_ranks;
  13         u32 datarate_mhz_high;
  14         u32 rank_gb;
  15         u32 clk_adjust;
  16         u32 wrlvl_start;
  17         u32 wrlvl_ctl_2;
  18         u32 wrlvl_ctl_3;
  19         u32 cpo_override;
  20         u32 write_data_delay;
  21         u32 force_2t;
  22 };
  23
  24 /*
  25  * These tables contain all valid speeds we want to override with board
  26  * specific parameters. datarate_mhz_high values need to be in ascending order
  27  * for each n_ranks group.
  28  */
  29 static const struct board_specific_parameters udimm0[] = {
  30         /*
  31          * memory controller 0
  32          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
  33          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
  34          */
  35 #ifdef CONFIG_SYS_FSL_DDR4
  36         {1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
  37         {1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
  38         {1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
  39 #endif
  40         {}
  41 };
  42
  43 static const struct board_specific_parameters *udimms[] = {
  44         udimm0,
  45 };
  46
  47 #ifndef CONFIG_SYS_DDR_RAW_TIMING
  48 fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
  49         .cs[0].bnds = 0x0000007F,
  50         .cs[1].bnds = 0,
  51         .cs[2].bnds = 0,
  52         .cs[3].bnds = 0,
  53         .cs[0].config = 0x80040322,
  54         .cs[0].config_2 = 0,
  55         .cs[1].config = 0,
  56         .cs[1].config_2 = 0,
  57         .cs[2].config = 0,
  58         .cs[3].config = 0,
  59         .timing_cfg_3 = 0x010C1000,
  60         .timing_cfg_0 = 0x91550018,
  61         .timing_cfg_1 = 0xBBB48C42,
  62         .timing_cfg_2 = 0x0048C111,
  63         .ddr_sdram_cfg = 0xC50C0008,
  64         .ddr_sdram_cfg_2 = 0x00401100,
  65         .ddr_sdram_cfg_3 = 0,
  66         .ddr_sdram_mode = 0x03010210,
  67         .ddr_sdram_mode_2 = 0,
  68         .ddr_sdram_mode_3 = 0x00010210,
  69         .ddr_sdram_mode_4 = 0,
  70         .ddr_sdram_mode_5 = 0x00010210,
  71         .ddr_sdram_mode_6 = 0,
  72         .ddr_sdram_mode_7 = 0x00010210,
  73         .ddr_sdram_mode_8 = 0,
  74         .ddr_sdram_mode_9 = 0x00000500,
  75         .ddr_sdram_mode_10 = 0x04000000,
  76         .ddr_sdram_mode_11 = 0x00000400,
  77         .ddr_sdram_mode_12 = 0x04000000,
  78         .ddr_sdram_mode_13 = 0x00000400,
  79         .ddr_sdram_mode_14 = 0x04000000,
  80         .ddr_sdram_mode_15 = 0x00000400,
  81         .ddr_sdram_mode_16 = 0x04000000,
  82         .ddr_sdram_interval = 0x18600618,
  83         .ddr_data_init = 0xDEADBEEF,
  84         .ddr_sdram_clk_cntl = 0x03000000,
  85         .ddr_init_addr = 0,
  86         .ddr_init_ext_addr = 0,
  87         .timing_cfg_4 = 0x00000002,
  88         .timing_cfg_5 = 0x03401400,
  89         .timing_cfg_6 = 0,
  90         .timing_cfg_7 = 0x13300000,
  91         .timing_cfg_8 = 0x02115600,
  92         .timing_cfg_9 = 0,
  93         .ddr_zq_cntl = 0x8A090705,
  94         .ddr_wrlvl_cntl = 0x8675F607,
  95         .ddr_wrlvl_cntl_2 = 0x07090800,
  96         .ddr_wrlvl_cntl_3 = 0,
  97         .ddr_sr_cntr = 0,
  98         .ddr_sdram_rcw_1 = 0,
  99         .ddr_sdram_rcw_2 = 0,
 100         .ddr_cdr1 = 0x80040000,
 101         .ddr_cdr2 = 0x0000A181,
 102         .dq_map_0 = 0,
 103         .dq_map_1 = 0,
 104         .dq_map_2 = 0,
 105         .dq_map_3 = 0,
 106         .debug[28] = 0x00700046,
 107
 108 };
 109
 110 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 111         {1550, 1650, &ddr_cfg_regs_1600},
 112         {0, 0, NULL}
 113 };
 114
 115 #endif
 116 #endif