1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
7 #include <fsl_ddr_sdram.h>
8 #include <fsl_ddr_dimm_params.h>
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
13 #include <asm/arch/clock.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 void fsl_ddr_board_options(memctl_options_t *popts,
19 unsigned int ctrl_num)
21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25 printf("Not supported controller number %d\n", ctrl_num);
33 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
34 * freqency and n_banks specified in board_specific_parameters table.
36 ddr_freq = get_ddr_freq(0) / 1000000;
37 while (pbsp->datarate_mhz_high) {
38 if (pbsp->n_ranks == pdimm->n_ranks) {
39 if (ddr_freq <= pbsp->datarate_mhz_high) {
40 popts->clk_adjust = pbsp->clk_adjust;
41 popts->wrlvl_start = pbsp->wrlvl_start;
42 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
43 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
44 popts->cpo_override = pbsp->cpo_override;
45 popts->write_data_delay =
46 pbsp->write_data_delay;
55 printf("Error: board specific timing not found for %lu MT/s\n",
57 printf("Trying to use the highest speed (%u) parameters\n",
58 pbsp_highest->datarate_mhz_high);
59 popts->clk_adjust = pbsp_highest->clk_adjust;
60 popts->wrlvl_start = pbsp_highest->wrlvl_start;
61 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
62 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 panic("DIMM is not supported by this board");
67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
68 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
70 /* force DDR bus width to 32 bits */
71 popts->data_bus_width = 1;
72 popts->otf_burst_chop_en = 0;
73 popts->burst_length = DDR_BL8;
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
79 popts->half_strength_driver_enable = 1;
81 * Write leveling override
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
87 * Rtt and Rtt_WR override
89 popts->rtt_override = 0;
91 /* Enable ZQ calibration */
94 /* optimize cpo for erratum A-009942 */
95 popts->cpo_sample = 0x46;
97 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
98 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
99 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
102 /* DDR model number: MT40A512M8HX-093E */
103 #ifdef CONFIG_SYS_DDR_RAW_TIMING
104 dimm_params_t ddr_raw_timing = {
106 .rank_density = 2147483648u,
107 .capacity = 2147483648u,
108 .primary_sdram_width = 32,
110 .registered_dimm = 0,
115 .bank_group_bits = 2,
117 .burst_lengths_bitmask = 0x0c,
121 .caslat_x = 0x000DFA00,
134 .refresh_rate_ps = 7800000,
135 .dq_mapping[0] = 0x0,
136 .dq_mapping[1] = 0x0,
137 .dq_mapping[2] = 0x0,
138 .dq_mapping[3] = 0x0,
139 .dq_mapping[4] = 0x0,
140 .dq_mapping[5] = 0x0,
141 .dq_mapping[6] = 0x0,
142 .dq_mapping[7] = 0x0,
143 .dq_mapping[8] = 0x0,
144 .dq_mapping[9] = 0x0,
145 .dq_mapping[10] = 0x0,
146 .dq_mapping[11] = 0x0,
147 .dq_mapping[12] = 0x0,
148 .dq_mapping[13] = 0x0,
149 .dq_mapping[14] = 0x0,
150 .dq_mapping[15] = 0x0,
151 .dq_mapping[16] = 0x0,
152 .dq_mapping[17] = 0x0,
156 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
157 unsigned int controller_number,
158 unsigned int dimm_number)
160 static const char dimm_model[] = "Fixed DDR on board";
162 if (((controller_number == 0) && (dimm_number == 0)) ||
163 ((controller_number == 1) && (dimm_number == 0))) {
164 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
165 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
166 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
173 phys_size_t fixed_sdram(void)
177 fsl_ddr_cfg_regs_t ddr_cfg_regs;
178 phys_size_t ddr_size;
179 ulong ddr_freq, ddr_freq_mhz;
181 ddr_freq = get_ddr_freq(0);
182 ddr_freq_mhz = ddr_freq / 1000000;
184 printf("Configuring DDR for %s MT/s data rate\n",
185 strmhz(buf, ddr_freq));
187 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
188 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
189 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
190 memcpy(&ddr_cfg_regs,
191 fixed_ddr_parm_0[i].ddr_settings,
192 sizeof(ddr_cfg_regs));
197 if (fixed_ddr_parm_0[i].max_freq == 0)
198 panic("Unsupported DDR data rate %s MT/s data rate\n",
199 strmhz(buf, ddr_freq));
201 ddr_size = (phys_size_t)2048 * 1024 * 1024;
202 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
208 #ifdef CONFIG_TFABOOT
209 int fsl_initdram(void)
211 gd->ram_size = tfa_get_dram_size();
213 #ifdef CONFIG_SYS_DDR_RAW_TIMING
214 gd->ram_size = fsl_ddr_sdram_size();
216 gd->ram_size = 0x80000000;
221 int fsl_initdram(void)
223 phys_size_t dram_size;
225 #ifdef CONFIG_SYS_DDR_RAW_TIMING
226 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
227 puts("Initializing DDR....\n");
228 dram_size = fsl_ddr_sdram();
230 dram_size = fsl_ddr_sdram_size();
233 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
234 puts("Initialzing DDR using fixed setting\n");
235 dram_size = fixed_sdram();
237 gd->ram_size = 0x80000000;
242 erratum_a008850_post();
244 #ifdef CONFIG_FSL_DEEP_SLEEP
245 fsl_dp_ddr_restore();
248 gd->ram_size = dram_size;