1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor
5 * Freescale LS1043ARDB board-specific CPLD controlling supports.
13 u8 cpld_read(unsigned int reg)
15 void *p = (void *)CONFIG_SYS_CPLD_BASE;
20 void cpld_write(unsigned int reg, u8 value)
22 void *p = (void *)CONFIG_SYS_CPLD_BASE;
24 out_8(p + reg, value);
27 /* Set the boot bank to the alternate bank */
28 void cpld_set_altbank(void)
30 u16 reg = CPLD_CFG_RCW_SRC_NOR;
31 u8 reg4 = CPLD_READ(soft_mux_on);
32 u8 reg5 = (u8)(reg >> 1);
33 u8 reg6 = (u8)(reg & 1);
34 u8 reg7 = CPLD_READ(vbank);
38 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
40 CPLD_WRITE(cfg_rcw_src1, reg5);
41 CPLD_WRITE(cfg_rcw_src2, reg6);
43 reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
44 CPLD_WRITE(vbank, reg7);
46 CPLD_WRITE(system_rst, 1);
49 /* Set the boot bank to the default bank */
50 void cpld_set_defbank(void)
52 u16 reg = CPLD_CFG_RCW_SRC_NOR;
53 u8 reg4 = CPLD_READ(soft_mux_on);
54 u8 reg5 = (u8)(reg >> 1);
55 u8 reg6 = (u8)(reg & 1);
59 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
61 CPLD_WRITE(cfg_rcw_src1, reg5);
62 CPLD_WRITE(cfg_rcw_src2, reg6);
66 CPLD_WRITE(system_rst, 1);
69 void cpld_set_nand(void)
71 u16 reg = CPLD_CFG_RCW_SRC_NAND;
72 u8 reg5 = (u8)(reg >> 1);
73 u8 reg6 = (u8)(reg & 1);
77 CPLD_WRITE(soft_mux_on, 1);
79 CPLD_WRITE(cfg_rcw_src1, reg5);
80 CPLD_WRITE(cfg_rcw_src2, reg6);
82 CPLD_WRITE(system_rst, 1);
85 void cpld_set_sd(void)
87 u16 reg = CPLD_CFG_RCW_SRC_SD;
88 u8 reg5 = (u8)(reg >> 1);
89 u8 reg6 = (u8)(reg & 1);
93 CPLD_WRITE(soft_mux_on, 1);
95 CPLD_WRITE(cfg_rcw_src1, reg5);
96 CPLD_WRITE(cfg_rcw_src2, reg6);
98 CPLD_WRITE(system_rst, 1);
101 static void cpld_dump_regs(void)
103 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
104 printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
105 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
106 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
107 printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
108 printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
109 printf("vbank = %x\n", CPLD_READ(vbank));
110 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
111 printf("uart_sel = %x\n", CPLD_READ(uart_sel));
112 printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
113 printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
114 printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
115 printf("status_led = %x\n", CPLD_READ(status_led));
120 void cpld_rev_bit(unsigned char *value)
127 for (i = 1; i <= 7; i++) {
136 int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
141 return cmd_usage(cmdtp);
143 if (strcmp(argv[1], "reset") == 0) {
144 if (strcmp(argv[2], "altbank") == 0)
146 else if (strcmp(argv[2], "nand") == 0)
148 else if (strcmp(argv[2], "sd") == 0)
153 } else if (strcmp(argv[1], "dump") == 0) {
157 rc = cmd_usage(cmdtp);
164 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
165 "Reset the board or alternate bank",
166 "reset: reset to default bank\n"
167 "cpld reset altbank: reset to alternate bank\n"
168 "cpld reset nand: reset to boot from NAND flash\n"
169 "cpld reset sd: reset to boot from SD card\n"
171 "cpld dump - display the CPLD registers\n"