1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/ppa.h>
17 #include <asm/arch/fdt.h>
18 #include <asm/arch/mmu.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/soc.h>
21 #include <asm/arch-fsl-layerscape/fsl_icid.h>
27 #include <fsl_esdhc.h>
31 #include "../common/qixis.h"
32 #include "ls1043aqds_qixis.h"
34 DECLARE_GLOBAL_DATA_PTR;
40 /* LS1043AQDS serdes mux */
41 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
42 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
43 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
44 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
45 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
46 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
47 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
48 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
49 #define CFG_UART_MUX_MASK 0x6
50 #define CFG_UART_MUX_SHIFT 1
51 #define CFG_LPUART_EN 0x1
54 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
58 CONFIG_SYS_NOR0_CSPR_EXT,
72 CONFIG_SYS_NOR1_CSPR_EXT,
85 CONFIG_SYS_NAND_CSPR_EXT,
86 CONFIG_SYS_NAND_AMASK,
89 CONFIG_SYS_NAND_FTIM0,
90 CONFIG_SYS_NAND_FTIM1,
91 CONFIG_SYS_NAND_FTIM2,
98 CONFIG_SYS_FPGA_CSPR_EXT,
99 CONFIG_SYS_FPGA_AMASK,
100 CONFIG_SYS_FPGA_CSOR,
102 CONFIG_SYS_FPGA_FTIM0,
103 CONFIG_SYS_FPGA_FTIM1,
104 CONFIG_SYS_FPGA_FTIM2,
105 CONFIG_SYS_FPGA_FTIM3
110 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
113 CONFIG_SYS_NAND_CSPR,
114 CONFIG_SYS_NAND_CSPR_EXT,
115 CONFIG_SYS_NAND_AMASK,
116 CONFIG_SYS_NAND_CSOR,
118 CONFIG_SYS_NAND_FTIM0,
119 CONFIG_SYS_NAND_FTIM1,
120 CONFIG_SYS_NAND_FTIM2,
121 CONFIG_SYS_NAND_FTIM3
126 CONFIG_SYS_NOR0_CSPR,
127 CONFIG_SYS_NOR0_CSPR_EXT,
128 CONFIG_SYS_NOR_AMASK,
131 CONFIG_SYS_NOR_FTIM0,
132 CONFIG_SYS_NOR_FTIM1,
133 CONFIG_SYS_NOR_FTIM2,
139 CONFIG_SYS_NOR1_CSPR,
140 CONFIG_SYS_NOR1_CSPR_EXT,
141 CONFIG_SYS_NOR_AMASK,
144 CONFIG_SYS_NOR_FTIM0,
145 CONFIG_SYS_NOR_FTIM1,
146 CONFIG_SYS_NOR_FTIM2,
152 CONFIG_SYS_FPGA_CSPR,
153 CONFIG_SYS_FPGA_CSPR_EXT,
154 CONFIG_SYS_FPGA_AMASK,
155 CONFIG_SYS_FPGA_CSOR,
157 CONFIG_SYS_FPGA_FTIM0,
158 CONFIG_SYS_FPGA_FTIM1,
159 CONFIG_SYS_FPGA_FTIM2,
160 CONFIG_SYS_FPGA_FTIM3
165 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
167 enum boot_src src = get_boot_src();
169 if (src == BOOT_SOURCE_IFC_NAND)
170 regs_info->regs = ifc_cfg_nand_boot;
172 regs_info->regs = ifc_cfg_nor_boot;
173 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
179 #ifdef CONFIG_TFABOOT
180 enum boot_src src = get_boot_src();
183 #ifndef CONFIG_SD_BOOT
187 puts("Board: LS1043AQDS, boot from ");
189 #ifdef CONFIG_TFABOOT
190 if (src == BOOT_SOURCE_SD_MMC)
195 #ifdef CONFIG_SD_BOOT
198 sw = QIXIS_READ(brdcfg[0]);
199 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
202 printf("vBank: %d\n", sw);
210 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
213 #ifdef CONFIG_TFABOOT
216 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
217 QIXIS_READ(id), QIXIS_READ(arch));
219 printf("FPGA: v%d (%s), build %d\n",
220 (int)QIXIS_READ(scver), qixis_read_tag(buf),
221 (int)qixis_read_minor());
226 bool if_board_diff_clk(void)
228 u8 diff_conf = QIXIS_READ(brdcfg[11]);
230 return diff_conf & 0x40;
233 unsigned long get_board_sys_clk(void)
235 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
237 switch (sysclk_conf & 0x0f) {
238 case QIXIS_SYSCLK_64:
240 case QIXIS_SYSCLK_83:
242 case QIXIS_SYSCLK_100:
244 case QIXIS_SYSCLK_125:
246 case QIXIS_SYSCLK_133:
248 case QIXIS_SYSCLK_150:
250 case QIXIS_SYSCLK_160:
252 case QIXIS_SYSCLK_166:
259 unsigned long get_board_ddr_clk(void)
261 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
263 if (if_board_diff_clk())
264 return get_board_sys_clk();
265 switch ((ddrclk_conf & 0x30) >> 4) {
266 case QIXIS_DDRCLK_100:
268 case QIXIS_DDRCLK_125:
270 case QIXIS_DDRCLK_133:
277 int select_i2c_ch_pca9547(u8 ch, int bus_num)
284 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
287 printf("%s: Cannot find udev for a bus %d\n", __func__,
291 ret = dm_i2c_write(dev, 0, &ch, 1);
293 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
296 puts("PCA: failed to select proper channel\n");
306 * When resuming from deep sleep, the I2C channel may not be
307 * in the default channel. So, switch to the default channel
308 * before accessing DDR SPD.
310 * PCA9547 mount on I2C1 bus
312 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
314 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
315 defined(CONFIG_SPL_BUILD)
316 /* This will break-before-make MMU for DDR */
317 update_early_mmu_table();
323 int i2c_multiplexer_select_vid_channel(u8 channel)
325 return select_i2c_ch_pca9547(channel, 0);
328 void board_retimer_init(void)
333 /* Retimer is connected to I2C1_CH7_CH5 */
334 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
340 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
343 printf("%s: Cannot find udev for a bus %d\n", __func__,
347 dm_i2c_write(dev, 0, ®, 1);
349 /* Access to Control/Shared register */
350 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
353 printf("%s: Cannot find udev for a bus %d\n", __func__,
359 dm_i2c_write(dev, 0xff, ®, 1);
361 /* Read device revision and ID */
362 dm_i2c_read(dev, 1, ®, 1);
363 debug("Retimer version id = 0x%x\n", reg);
365 /* Enable Broadcast. All writes target all channel register sets */
367 dm_i2c_write(dev, 0xff, ®, 1);
369 /* Reset Channel Registers */
370 dm_i2c_read(dev, 0, ®, 1);
372 dm_i2c_write(dev, 0, ®, 1);
374 /* Enable override divider select and Enable Override Output Mux */
375 dm_i2c_read(dev, 9, ®, 1);
377 dm_i2c_write(dev, 9, ®, 1);
379 /* Select VCO Divider to full rate (000) */
380 dm_i2c_read(dev, 0x18, ®, 1);
382 dm_i2c_write(dev, 0x18, ®, 1);
384 /* Selects active PFD MUX Input as Re-timed Data (001) */
385 dm_i2c_read(dev, 0x1e, ®, 1);
388 dm_i2c_write(dev, 0x1e, ®, 1);
390 /* Set data rate as 10.3125 Gbps */
392 dm_i2c_write(dev, 0x60, ®, 1);
394 dm_i2c_write(dev, 0x61, ®, 1);
396 dm_i2c_write(dev, 0x62, ®, 1);
398 dm_i2c_write(dev, 0x63, ®, 1);
400 dm_i2c_write(dev, 0x64, ®, 1);
402 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
404 /* Access to Control/Shared register */
406 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
408 /* Read device revision and ID */
409 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
410 debug("Retimer version id = 0x%x\n", reg);
412 /* Enable Broadcast. All writes target all channel register sets */
414 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
416 /* Reset Channel Registers */
417 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
419 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
421 /* Enable override divider select and Enable Override Output Mux */
422 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
424 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
426 /* Select VCO Divider to full rate (000) */
427 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
429 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
431 /* Selects active PFD MUX Input as Re-timed Data (001) */
432 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
435 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
437 /* Set data rate as 10.3125 Gbps */
439 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
441 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
443 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
445 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
447 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
450 /* Return the default channel */
451 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
454 int board_early_init_f(void)
456 #ifdef CONFIG_HAS_FSL_XHCI_USB
457 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
464 #ifdef CONFIG_SYS_I2C
465 #ifdef CONFIG_SYS_I2C_EARLY_INIT
469 fsl_lsch2_early_init_f();
471 #ifdef CONFIG_HAS_FSL_XHCI_USB
472 out_be32(&scfg->rcwpmuxcr0, 0x3333);
473 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
475 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
476 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
477 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
478 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
482 /* We use lpuart0 as system console */
483 uart = QIXIS_READ(brdcfg[14]);
484 uart &= ~CFG_UART_MUX_MASK;
485 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
486 QIXIS_WRITE(brdcfg[14], uart);
492 #ifdef CONFIG_FSL_DEEP_SLEEP
493 /* determine if it is a warm boot */
494 bool is_warm_boot(void)
496 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
497 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
499 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
506 int config_board_mux(int ctrl_type)
510 reg14 = QIXIS_READ(brdcfg[14]);
514 reg14 = (reg14 & (~0x30)) | 0x20;
517 puts("Unsupported mux interface type\n");
521 QIXIS_WRITE(brdcfg[14], reg14);
526 int config_serdes_mux(void)
532 #ifdef CONFIG_MISC_INIT_R
533 int misc_init_r(void)
535 if (hwconfig("gpio"))
536 config_board_mux(MUX_TYPE_GPIO);
544 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
548 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
549 board_retimer_init();
551 #ifdef CONFIG_SYS_FSL_SERDES
555 #ifdef CONFIG_FSL_LS_PPA
562 #ifdef CONFIG_OF_BOARD_SETUP
563 int ft_board_setup(void *blob, bd_t *bd)
565 u64 base[CONFIG_NR_DRAM_BANKS];
566 u64 size[CONFIG_NR_DRAM_BANKS];
569 /* fixup DT for the two DDR banks */
570 base[0] = gd->bd->bi_dram[0].start;
571 size[0] = gd->bd->bi_dram[0].size;
572 base[1] = gd->bd->bi_dram[1].start;
573 size[1] = gd->bd->bi_dram[1].size;
575 fdt_fixup_memory_banks(blob, base, size, 2);
576 ft_cpu_setup(blob, bd);
578 #ifdef CONFIG_SYS_DPAA_FMAN
579 #ifndef CONFIG_DM_ETH
580 fdt_fixup_fman_ethernet(blob);
582 fdt_fixup_board_enet(blob);
585 fdt_fixup_icid(blob);
587 reg = QIXIS_READ(brdcfg[0]);
588 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
590 /* Disable IFC if QSPI is enabled */
592 do_fixup_by_compat(blob, "fsl,ifc",
593 "status", "disabled", 8 + 1, 1);
599 u8 flash_read8(void *addr)
601 return __raw_readb(addr + 1);
604 void flash_write16(u16 val, void *addr)
606 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
608 __raw_writew(shftval, addr);
611 u16 flash_read16(void *addr)
613 u16 val = __raw_readw(addr);
615 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
618 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
619 void *env_sf_get_env_addr(void)
621 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);