2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
21 #include <fsl_esdhc.h>
25 #include "../common/qixis.h"
26 #include "ls1043aqds_qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
34 /* LS1043AQDS serdes mux */
35 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
36 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
37 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
38 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
39 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
40 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
41 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
42 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
43 #define CFG_UART_MUX_MASK 0x6
44 #define CFG_UART_MUX_SHIFT 1
45 #define CFG_LPUART_EN 0x1
50 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
54 puts("Board: LS1043AQDS, boot from ");
58 #elif defined(CONFIG_QSPI_BOOT)
61 sw = QIXIS_READ(brdcfg[0]);
62 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
65 printf("vBank: %d\n", sw);
73 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
76 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
77 QIXIS_READ(id), QIXIS_READ(arch));
79 printf("FPGA: v%d (%s), build %d\n",
80 (int)QIXIS_READ(scver), qixis_read_tag(buf),
81 (int)qixis_read_minor());
86 bool if_board_diff_clk(void)
88 u8 diff_conf = QIXIS_READ(brdcfg[11]);
90 return diff_conf & 0x40;
93 unsigned long get_board_sys_clk(void)
95 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
97 switch (sysclk_conf & 0x0f) {
100 case QIXIS_SYSCLK_83:
102 case QIXIS_SYSCLK_100:
104 case QIXIS_SYSCLK_125:
106 case QIXIS_SYSCLK_133:
108 case QIXIS_SYSCLK_150:
110 case QIXIS_SYSCLK_160:
112 case QIXIS_SYSCLK_166:
119 unsigned long get_board_ddr_clk(void)
121 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
123 if (if_board_diff_clk())
124 return get_board_sys_clk();
125 switch ((ddrclk_conf & 0x30) >> 4) {
126 case QIXIS_DDRCLK_100:
128 case QIXIS_DDRCLK_125:
130 case QIXIS_DDRCLK_133:
137 int select_i2c_ch_pca9547(u8 ch)
141 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
143 puts("PCA: failed to select proper channel\n");
153 * When resuming from deep sleep, the I2C channel may not be
154 * in the default channel. So, switch to the default channel
155 * before accessing DDR SPD.
157 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
158 gd->ram_size = initdram(0);
163 int i2c_multiplexer_select_vid_channel(u8 channel)
165 return select_i2c_ch_pca9547(channel);
168 void board_retimer_init(void)
172 /* Retimer is connected to I2C1_CH7_CH5 */
174 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
176 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
178 /* Access to Control/Shared register */
180 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
182 /* Read device revision and ID */
183 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
184 debug("Retimer version id = 0x%x\n", reg);
186 /* Enable Broadcast. All writes target all channel register sets */
188 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
190 /* Reset Channel Registers */
191 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
193 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
195 /* Enable override divider select and Enable Override Output Mux */
196 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
198 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
200 /* Select VCO Divider to full rate (000) */
201 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
203 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
205 /* Selects active PFD MUX Input as Re-timed Data (001) */
206 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
209 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
211 /* Set data rate as 10.3125 Gbps */
213 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
215 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
217 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
219 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
221 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
224 int board_early_init_f(void)
229 fsl_lsch2_early_init_f();
231 /* We use lpuart0 as system console */
232 uart = QIXIS_READ(brdcfg[14]);
233 uart &= ~CFG_UART_MUX_MASK;
234 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
235 QIXIS_WRITE(brdcfg[14], uart);
241 #ifdef CONFIG_FSL_DEEP_SLEEP
242 /* determine if it is a warm boot */
243 bool is_warm_boot(void)
245 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
246 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
248 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
255 int config_board_mux(int ctrl_type)
259 reg14 = QIXIS_READ(brdcfg[14]);
263 reg14 = (reg14 & (~0x30)) | 0x20;
266 puts("Unsupported mux interface type\n");
270 QIXIS_WRITE(brdcfg[14], reg14);
275 int config_serdes_mux(void)
281 #ifdef CONFIG_MISC_INIT_R
282 int misc_init_r(void)
284 if (hwconfig("gpio"))
285 config_board_mux(MUX_TYPE_GPIO);
293 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
294 CONFIG_SYS_CCI400_ADDR;
296 /* Set CCI-400 control override register to enable barrier
298 out_le32(&cci->ctrl_ord,
299 CCI400_CTRLORD_EN_BARRIER);
301 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
302 board_retimer_init();
304 #ifdef CONFIG_SYS_FSL_SERDES
308 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
309 enable_layerscape_ns_access();
312 #ifdef CONFIG_ENV_IS_NOWHERE
313 gd->env_addr = (ulong)&default_environment[0];
318 #ifdef CONFIG_OF_BOARD_SETUP
319 int ft_board_setup(void *blob, bd_t *bd)
321 u64 base[CONFIG_NR_DRAM_BANKS];
322 u64 size[CONFIG_NR_DRAM_BANKS];
324 /* fixup DT for the two DDR banks */
325 base[0] = gd->bd->bi_dram[0].start;
326 size[0] = gd->bd->bi_dram[0].size;
327 base[1] = gd->bd->bi_dram[1].start;
328 size[1] = gd->bd->bi_dram[1].size;
330 fdt_fixup_memory_banks(blob, base, size, 2);
331 ft_cpu_setup(blob, bd);
333 #ifdef CONFIG_SYS_DPAA_FMAN
334 fdt_fixup_fman_ethernet(blob);
335 fdt_fixup_board_enet(blob);
341 u8 flash_read8(void *addr)
343 return __raw_readb(addr + 1);
346 void flash_write16(u16 val, void *addr)
348 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
350 __raw_writew(shftval, addr);
353 u16 flash_read16(void *addr)
355 u16 val = __raw_readw(addr);
357 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);