board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <i2c.h>
  17 #include <asm/arch/soc.h>
  18 #ifdef CONFIG_FSL_LS_PPA
  19 #include <asm/arch/ppa.h>
  20 #endif
  21 #include <fsl_immap.h>
  22 #include <netdev.h>
  23
  24 #include <fdtdec.h>
  25 #include <miiphy.h>
  26 #include "../common/qixis.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int config_board_mux(void)
  31 {
  32 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  33         u8 reg;
  34
  35         reg = QIXIS_READ(brdcfg[13]);
  36         /* Field| Function
  37          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  38          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  39          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  40          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  41          */
  42         reg &= ~(0xf0);
  43         reg |= 0xb0;
  44         QIXIS_WRITE(brdcfg[13], reg);
  45
  46         reg = QIXIS_READ(brdcfg[15]);
  47         /* Field| Function
  48          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  49          * CAN1 | 0= CAN #1 transceiver enabled
  50          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  51          * CAN2 | 0= CAN #2 transceiver enabled
  52          */
  53         reg &= ~(0xc0);
  54         QIXIS_WRITE(brdcfg[15], reg);
  55 #endif
  56         return 0;
  57 }
  58
  59 int board_init(void)
  60 {
  61 #ifdef CONFIG_ENV_IS_NOWHERE
  62         gd->env_addr = (ulong)&default_environment[0];
  63 #endif
  64
  65 #ifdef CONFIG_FSL_LS_PPA
  66         ppa_init();
  67 #endif
  68
  69 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  70         pci_init();
  71 #endif
  72
  73 #if defined(CONFIG_TARGET_LS1028ARDB)
  74         u8 val = I2C_MUX_CH_DEFAULT;
  75
  76 #ifndef CONFIG_DM_I2C
  77         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  78 #else
  79         struct udevice *dev;
  80
  81         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  82                 dm_i2c_write(dev, 0x0b, &val, 1);
  83 #endif
  84
  85 #endif
  86         return 0;
  87 }
  88
  89 int board_eth_init(bd_t *bis)
  90 {
  91         return pci_eth_init(bis);
  92 }
  93
  94 #if defined(CONFIG_ARCH_MISC_INIT)
  95 int arch_misc_init(void)
  96 {
  97         config_board_mux();
  98
  99         return 0;
 100 }
 101 #endif
 102
 103 int board_early_init_f(void)
 104 {
 105 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 106         i2c_early_init_f();
 107 #endif
 108
 109         fsl_lsch3_early_init_f();
 110         return 0;
 111 }
 112
 113 void detail_board_ddr_info(void)
 114 {
 115         puts("\nDDR    ");
 116         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 117         print_ddr_info(0);
 118 }
 119
 120 #ifdef CONFIG_OF_BOARD_SETUP
 121 int ft_board_setup(void *blob, bd_t *bd)
 122 {
 123         u64 base[CONFIG_NR_DRAM_BANKS];
 124         u64 size[CONFIG_NR_DRAM_BANKS];
 125
 126         ft_cpu_setup(blob, bd);
 127
 128         /* fixup DT for the two GPP DDR banks */
 129         base[0] = gd->bd->bi_dram[0].start;
 130         size[0] = gd->bd->bi_dram[0].size;
 131         base[1] = gd->bd->bi_dram[1].start;
 132         size[1] = gd->bd->bi_dram[1].size;
 133
 134 #ifdef CONFIG_RESV_RAM
 135         /* reduce size if reserved memory is within this bank */
 136         if (gd->arch.resv_ram >= base[0] &&
 137             gd->arch.resv_ram < base[0] + size[0])
 138                 size[0] = gd->arch.resv_ram - base[0];
 139         else if (gd->arch.resv_ram >= base[1] &&
 140                  gd->arch.resv_ram < base[1] + size[1])
 141                 size[1] = gd->arch.resv_ram - base[1];
 142 #endif
 143
 144         fdt_fixup_memory_banks(blob, base, size, 2);
 145
 146         return 0;
 147 }
 148 #endif
 149
 150 #ifdef CONFIG_FSL_QIXIS
 151 int checkboard(void)
 152 {
 153 #ifdef CONFIG_TFABOOT
 154         enum boot_src src = get_boot_src();
 155 #endif
 156         u8 sw;
 157
 158         int clock;
 159         char *board;
 160         char buf[64] = {0};
 161         static const char *freq[6] = {"100.00", "125.00", "156.25",
 162                                         "161.13", "322.26", "100.00 SS"};
 163
 164         cpu_name(buf);
 165         /* find the board details */
 166         sw = QIXIS_READ(id);
 167
 168         switch (sw) {
 169         case 0x46:
 170                 board = "QDS";
 171                 break;
 172         case 0x47:
 173                 board = "RDB";
 174                 break;
 175         case 0x49:
 176                 board = "HSSI";
 177                 break;
 178         default:
 179                 board = "unknown";
 180                 break;
 181         }
 182
 183         sw = QIXIS_READ(arch);
 184         printf("Board: %s-%s, Version: %c, boot from ",
 185                buf, board, (sw & 0xf) + 'A' - 1);
 186
 187         sw = QIXIS_READ(brdcfg[0]);
 188         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 189
 190 #ifdef CONFIG_TFABOOT
 191         if (src == BOOT_SOURCE_SD_MMC) {
 192                 puts("SD\n");
 193         } else if (src == BOOT_SOURCE_SD_MMC2) {
 194                 puts("eMMC\n");
 195         } else {
 196 #endif
 197 #ifdef CONFIG_SD_BOOT
 198                 puts("SD\n");
 199 #elif defined(CONFIG_EMMC_BOOT)
 200                 puts("eMMC\n");
 201 #else
 202                 switch (sw) {
 203                 case 0:
 204                 case 4:
 205                         printf("NOR\n");
 206                         break;
 207                 case 1:
 208                         printf("NAND\n");
 209                         break;
 210                 default:
 211                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 212                         break;
 213                 }
 214 #endif
 215 #ifdef CONFIG_TFABOOT
 216         }
 217 #endif
 218
 219         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 220         puts("SERDES1 Reference : ");
 221
 222         sw = QIXIS_READ(brdcfg[2]);
 223 #ifdef CONFIG_TARGET_LS1028ARDB
 224         clock = (sw >> 6) & 3;
 225 #else
 226         clock = (sw >> 4) & 0xf;
 227 #endif
 228
 229         printf("Clock1 = %sMHz ", freq[clock]);
 230 #ifdef CONFIG_TARGET_LS1028ARDB
 231         clock = (sw >> 4) & 3;
 232 #else
 233         clock = sw & 0xf;
 234 #endif
 235         printf("Clock2 = %sMHz\n", freq[clock]);
 236
 237         return 0;
 238 }
 239 #endif