1 // SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
13 #include <linux/libfdt.h>
14 #include <env_internal.h>
15 #include <asm/arch-fsl-layerscape/soc.h>
16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
18 #include <asm/arch/soc.h>
19 #ifdef CONFIG_FSL_LS_PPA
20 #include <asm/arch/ppa.h>
22 #include <fsl_immap.h>
27 #include "../common/qixis.h"
28 #include "../drivers/net/fsl_enetc.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 int config_board_mux(void)
34 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
37 reg = QIXIS_READ(brdcfg[13]);
39 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
40 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
41 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
42 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
46 QIXIS_WRITE(brdcfg[13], reg);
48 reg = QIXIS_READ(brdcfg[15]);
50 * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
51 * CAN1 | 0= CAN #1 transceiver enabled
52 * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
53 * CAN2 | 0= CAN #2 transceiver enabled
56 QIXIS_WRITE(brdcfg[15], reg);
63 #ifdef CONFIG_ENV_IS_NOWHERE
64 gd->env_addr = (ulong)&default_environment[0];
67 #ifdef CONFIG_FSL_CAAM
71 #ifdef CONFIG_FSL_LS_PPA
75 #ifndef CONFIG_SYS_EARLY_PCI_INIT
79 #if defined(CONFIG_TARGET_LS1028ARDB)
80 u8 val = I2C_MUX_CH_DEFAULT;
83 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
87 if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
88 dm_i2c_write(dev, 0x0b, &val, 1);
92 #if defined(CONFIG_TARGET_LS1028ARDB)
95 reg = QIXIS_READ(brdcfg[4]);
98 * 3 | DisplayPort Power Enable (net DP_PWR_EN):
99 * DPPWR | 0= DP_PWR is enabled.
101 reg &= ~(DP_PWD_EN_DEFAULT_MASK);
102 QIXIS_WRITE(brdcfg[4], reg);
107 int board_eth_init(bd_t *bis)
109 return pci_eth_init(bis);
112 #if defined(CONFIG_ARCH_MISC_INIT)
113 int arch_misc_init(void)
121 int board_early_init_f(void)
123 #ifdef CONFIG_SYS_I2C_EARLY_INIT
127 fsl_lsch3_early_init_f();
131 void detail_board_ddr_info(void)
134 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
138 #ifdef CONFIG_OF_BOARD_SETUP
139 int ft_board_setup(void *blob, bd_t *bd)
141 u64 base[CONFIG_NR_DRAM_BANKS];
142 u64 size[CONFIG_NR_DRAM_BANKS];
144 ft_cpu_setup(blob, bd);
146 /* fixup DT for the two GPP DDR banks */
147 base[0] = gd->bd->bi_dram[0].start;
148 size[0] = gd->bd->bi_dram[0].size;
149 base[1] = gd->bd->bi_dram[1].start;
150 size[1] = gd->bd->bi_dram[1].size;
152 #ifdef CONFIG_RESV_RAM
153 /* reduce size if reserved memory is within this bank */
154 if (gd->arch.resv_ram >= base[0] &&
155 gd->arch.resv_ram < base[0] + size[0])
156 size[0] = gd->arch.resv_ram - base[0];
157 else if (gd->arch.resv_ram >= base[1] &&
158 gd->arch.resv_ram < base[1] + size[1])
159 size[1] = gd->arch.resv_ram - base[1];
162 fdt_fixup_memory_banks(blob, base, size, 2);
164 fdt_fixup_icid(blob);
166 #ifdef CONFIG_FSL_ENETC
167 fdt_fixup_enetc_mac(blob);
174 #ifdef CONFIG_FSL_QIXIS
177 #ifdef CONFIG_TFABOOT
178 enum boot_src src = get_boot_src();
185 static const char *freq[6] = {"100.00", "125.00", "156.25",
186 "161.13", "322.26", "100.00 SS"};
189 /* find the board details */
207 sw = QIXIS_READ(arch);
208 printf("Board: %s-%s, Version: %c, boot from ",
209 buf, board, (sw & 0xf) + 'A' - 1);
211 sw = QIXIS_READ(brdcfg[0]);
212 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
214 #ifdef CONFIG_TFABOOT
215 if (src == BOOT_SOURCE_SD_MMC) {
217 } else if (src == BOOT_SOURCE_SD_MMC2) {
221 #ifdef CONFIG_SD_BOOT
223 #elif defined(CONFIG_EMMC_BOOT)
235 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
239 #ifdef CONFIG_TFABOOT
243 printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
244 puts("SERDES1 Reference : ");
246 sw = QIXIS_READ(brdcfg[2]);
247 #ifdef CONFIG_TARGET_LS1028ARDB
248 clock = (sw >> 6) & 3;
250 clock = (sw >> 4) & 0xf;
253 printf("Clock1 = %sMHz ", freq[clock]);
254 #ifdef CONFIG_TARGET_LS1028ARDB
255 clock = (sw >> 4) & 3;
259 printf("Clock2 = %sMHz\n", freq[clock]);