board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17 #include <i2c.h>
  18 #include <asm/arch/soc.h>
  19 #ifdef CONFIG_FSL_LS_PPA
  20 #include <asm/arch/ppa.h>
  21 #endif
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24
  25 #include <fdtdec.h>
  26 #include <miiphy.h>
  27 #include "../common/qixis.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int config_board_mux(void)
  32 {
  33 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  34         u8 reg;
  35
  36         reg = QIXIS_READ(brdcfg[13]);
  37         /* Field| Function
  38          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  39          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  40          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  41          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  42          */
  43         reg &= ~(0xf0);
  44         reg |= 0xb0;
  45         QIXIS_WRITE(brdcfg[13], reg);
  46
  47         reg = QIXIS_READ(brdcfg[15]);
  48         /* Field| Function
  49          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  50          * CAN1 | 0= CAN #1 transceiver enabled
  51          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  52          * CAN2 | 0= CAN #2 transceiver enabled
  53          */
  54         reg &= ~(0xc0);
  55         QIXIS_WRITE(brdcfg[15], reg);
  56 #endif
  57         return 0;
  58 }
  59
  60 int board_init(void)
  61 {
  62 #ifdef CONFIG_ENV_IS_NOWHERE
  63         gd->env_addr = (ulong)&default_environment[0];
  64 #endif
  65
  66 #ifdef CONFIG_FSL_LS_PPA
  67         ppa_init();
  68 #endif
  69
  70 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  71         pci_init();
  72 #endif
  73
  74 #if defined(CONFIG_TARGET_LS1028ARDB)
  75         u8 val = I2C_MUX_CH_DEFAULT;
  76
  77 #ifndef CONFIG_DM_I2C
  78         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  79 #else
  80         struct udevice *dev;
  81
  82         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  83                 dm_i2c_write(dev, 0x0b, &val, 1);
  84 #endif
  85
  86 #endif
  87         return 0;
  88 }
  89
  90 int board_eth_init(bd_t *bis)
  91 {
  92         return pci_eth_init(bis);
  93 }
  94
  95 #if defined(CONFIG_ARCH_MISC_INIT)
  96 int arch_misc_init(void)
  97 {
  98         config_board_mux();
  99
 100         return 0;
 101 }
 102 #endif
 103
 104 int board_early_init_f(void)
 105 {
 106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 107         i2c_early_init_f();
 108 #endif
 109
 110         fsl_lsch3_early_init_f();
 111         return 0;
 112 }
 113
 114 void detail_board_ddr_info(void)
 115 {
 116         puts("\nDDR    ");
 117         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 118         print_ddr_info(0);
 119 }
 120
 121 #ifdef CONFIG_OF_BOARD_SETUP
 122 int ft_board_setup(void *blob, bd_t *bd)
 123 {
 124         u64 base[CONFIG_NR_DRAM_BANKS];
 125         u64 size[CONFIG_NR_DRAM_BANKS];
 126
 127         ft_cpu_setup(blob, bd);
 128
 129         /* fixup DT for the two GPP DDR banks */
 130         base[0] = gd->bd->bi_dram[0].start;
 131         size[0] = gd->bd->bi_dram[0].size;
 132         base[1] = gd->bd->bi_dram[1].start;
 133         size[1] = gd->bd->bi_dram[1].size;
 134
 135 #ifdef CONFIG_RESV_RAM
 136         /* reduce size if reserved memory is within this bank */
 137         if (gd->arch.resv_ram >= base[0] &&
 138             gd->arch.resv_ram < base[0] + size[0])
 139                 size[0] = gd->arch.resv_ram - base[0];
 140         else if (gd->arch.resv_ram >= base[1] &&
 141                  gd->arch.resv_ram < base[1] + size[1])
 142                 size[1] = gd->arch.resv_ram - base[1];
 143 #endif
 144
 145         fdt_fixup_memory_banks(blob, base, size, 2);
 146
 147         fdt_fixup_icid(blob);
 148
 149         return 0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_FSL_QIXIS
 154 int checkboard(void)
 155 {
 156 #ifdef CONFIG_TFABOOT
 157         enum boot_src src = get_boot_src();
 158 #endif
 159         u8 sw;
 160
 161         int clock;
 162         char *board;
 163         char buf[64] = {0};
 164         static const char *freq[6] = {"100.00", "125.00", "156.25",
 165                                         "161.13", "322.26", "100.00 SS"};
 166
 167         cpu_name(buf);
 168         /* find the board details */
 169         sw = QIXIS_READ(id);
 170
 171         switch (sw) {
 172         case 0x46:
 173                 board = "QDS";
 174                 break;
 175         case 0x47:
 176                 board = "RDB";
 177                 break;
 178         case 0x49:
 179                 board = "HSSI";
 180                 break;
 181         default:
 182                 board = "unknown";
 183                 break;
 184         }
 185
 186         sw = QIXIS_READ(arch);
 187         printf("Board: %s-%s, Version: %c, boot from ",
 188                buf, board, (sw & 0xf) + 'A' - 1);
 189
 190         sw = QIXIS_READ(brdcfg[0]);
 191         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 192
 193 #ifdef CONFIG_TFABOOT
 194         if (src == BOOT_SOURCE_SD_MMC) {
 195                 puts("SD\n");
 196         } else if (src == BOOT_SOURCE_SD_MMC2) {
 197                 puts("eMMC\n");
 198         } else {
 199 #endif
 200 #ifdef CONFIG_SD_BOOT
 201                 puts("SD\n");
 202 #elif defined(CONFIG_EMMC_BOOT)
 203                 puts("eMMC\n");
 204 #else
 205                 switch (sw) {
 206                 case 0:
 207                 case 4:
 208                         printf("NOR\n");
 209                         break;
 210                 case 1:
 211                         printf("NAND\n");
 212                         break;
 213                 default:
 214                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 215                         break;
 216                 }
 217 #endif
 218 #ifdef CONFIG_TFABOOT
 219         }
 220 #endif
 221
 222         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 223         puts("SERDES1 Reference : ");
 224
 225         sw = QIXIS_READ(brdcfg[2]);
 226 #ifdef CONFIG_TARGET_LS1028ARDB
 227         clock = (sw >> 6) & 3;
 228 #else
 229         clock = (sw >> 4) & 0xf;
 230 #endif
 231
 232         printf("Clock1 = %sMHz ", freq[clock]);
 233 #ifdef CONFIG_TARGET_LS1028ARDB
 234         clock = (sw >> 4) & 3;
 235 #else
 236         clock = sw & 0xf;
 237 #endif
 238         printf("Clock2 = %sMHz\n", freq[clock]);
 239
 240         return 0;
 241 }
 242 #endif