2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/pcie_layerscape.h>
15 #include <fsl_esdhc.h>
23 #include "../../../drivers/qe/qe.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define VERSION_MASK 0x00FF
30 #define BANK_MASK 0x0001
31 #define CONFIG_RESET 0x1
32 #define INIT_RESET 0x1
34 #define CPLD_SET_MUX_SERDES 0x20
35 #define CPLD_SET_BOOT_BANK 0x40
37 #define BOOT_FROM_UPPER_BANK 0x0
38 #define BOOT_FROM_LOWER_BANK 0x1
40 #define LANEB_SATA (0x01)
41 #define LANEB_SGMII1 (0x02)
42 #define LANEC_SGMII1 (0x04)
43 #define LANEC_PCIEX1 (0x08)
44 #define LANED_PCIEX2 (0x10)
45 #define LANED_SGMII2 (0x20)
47 #define MASK_LANE_B 0x1
48 #define MASK_LANE_C 0x2
49 #define MASK_LANE_D 0x4
50 #define MASK_SGMII 0x8
52 #define KEEP_STATUS 0x0
53 #define NEED_RESET 0x1
56 u8 cpld_ver; /* cpld revision */
57 u8 cpld_ver_sub; /* cpld sub revision */
58 u8 pcba_ver; /* pcb revision number */
59 u8 system_rst; /* reset system by cpld */
60 u8 soft_mux_on; /* CPLD override physical switches Enable */
61 u8 cfg_rcw_src1; /* Reset config word 1 */
62 u8 cfg_rcw_src2; /* Reset config word 2 */
63 u8 vbank; /* Flash bank selection Control */
64 u8 gpio; /* GPIO for TWR-ELEV */
67 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
68 u8 qe_lcd_mux; /* QE and LCD Selection */
69 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
70 u8 global_rst; /* reset with init CPLD reg to default */
71 u8 rev1; /* Reserved */
72 u8 rev2; /* Reserved */
75 static void convert_serdes_mux(int type, int need_reset);
79 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
81 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
82 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
83 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
84 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
85 in_8(&cpld_data->vbank) & BANK_MASK);
88 printf("soft_mux_on =%x\n",
89 in_8(&cpld_data->soft_mux_on));
90 printf("cfg_rcw_src1 =%x\n",
91 in_8(&cpld_data->cfg_rcw_src1));
92 printf("cfg_rcw_src2 =%x\n",
93 in_8(&cpld_data->cfg_rcw_src2));
95 in_8(&cpld_data->vbank));
97 in_8(&cpld_data->gpio));
98 printf("i2c3_ifc_mux =%x\n",
99 in_8(&cpld_data->i2c3_ifc_mux));
100 printf("mux_spi2 =%x\n",
101 in_8(&cpld_data->mux_spi2));
102 printf("can3_usb2_mux =%x\n",
103 in_8(&cpld_data->can3_usb2_mux));
104 printf("qe_lcd_mux =%x\n",
105 in_8(&cpld_data->qe_lcd_mux));
106 printf("serdes_mux =%x\n",
107 in_8(&cpld_data->serdes_mux));
113 puts("Board: LS1021ATWR\n");
119 void ddrmc_init(void)
121 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
123 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
125 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
126 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
128 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
129 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
130 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
131 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
132 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
133 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
135 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
137 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
138 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
140 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
142 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
144 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
145 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
147 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
148 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
150 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
151 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
153 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
155 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
160 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
164 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
168 #ifdef CONFIG_FSL_ESDHC
169 struct fsl_esdhc_cfg esdhc_cfg[1] = {
170 {CONFIG_SYS_FSL_ESDHC_ADDR},
173 int board_mmc_init(bd_t *bis)
175 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
177 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
181 #ifdef CONFIG_TSEC_ENET
182 int board_eth_init(bd_t *bis)
184 struct fsl_pq_mdio_info mdio_info;
185 struct tsec_info_struct tsec_info[4];
189 SET_STD_TSEC_INFO(tsec_info[num], 1);
190 if (is_serdes_configured(SGMII_TSEC1)) {
191 puts("eTSEC1 is in sgmii mode.\n");
192 tsec_info[num].flags |= TSEC_SGMII;
197 SET_STD_TSEC_INFO(tsec_info[num], 2);
198 if (is_serdes_configured(SGMII_TSEC2)) {
199 puts("eTSEC2 is in sgmii mode.\n");
200 tsec_info[num].flags |= TSEC_SGMII;
205 SET_STD_TSEC_INFO(tsec_info[num], 3);
209 printf("No TSECs initialized\n");
213 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
214 mdio_info.name = DEFAULT_MII_NAME;
215 fsl_pq_mdio_init(bis, &mdio_info);
217 tsec_eth_init(bis, tsec_info, num);
219 return pci_eth_init(bis);
223 int config_serdes_mux(void)
225 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
226 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
228 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
231 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
232 convert_serdes_mux(LANED_PCIEX2 |
233 LANEC_PCIEX1, KEEP_STATUS);
236 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
237 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
238 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
241 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
242 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
243 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
246 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
247 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
248 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
255 int board_early_init_f(void)
257 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
259 #ifdef CONFIG_TSEC_ENET
260 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
261 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
264 #ifdef CONFIG_FSL_IFC
265 init_early_memctl_regs();
268 #ifdef CONFIG_FSL_DCU_FB
269 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
275 #ifdef CONFIG_SPL_BUILD
276 void board_init_f(ulong dummy)
278 /* Set global data pointer */
282 memset(__bss_start, 0, __bss_end - __bss_start);
286 preloader_console_init();
290 board_init_r(NULL, 0);
296 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
299 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
300 * All transactions are treated as non-shareable
302 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
303 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
304 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
306 #ifndef CONFIG_SYS_FSL_NO_SERDES
318 #if defined(CONFIG_MISC_INIT_R)
319 int misc_init_r(void)
321 #ifdef CONFIG_FSL_CAAM
327 int ft_board_setup(void *blob, bd_t *bd)
329 ft_cpu_setup(blob, bd);
331 #ifdef CONFIG_PCIE_LAYERSCAPE
332 ft_pcie_setup(blob, bd);
338 u8 flash_read8(void *addr)
340 return __raw_readb(addr + 1);
343 void flash_write16(u16 val, void *addr)
345 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
347 __raw_writew(shftval, addr);
350 u16 flash_read16(void *addr)
352 u16 val = __raw_readw(addr);
354 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
357 static void convert_flash_bank(char bank)
359 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
361 printf("Now switch to boot from flash bank %d.\n", bank);
362 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
363 cpld_data->vbank = bank;
365 printf("Reset board to enable configuration.\n");
366 cpld_data->system_rst = CONFIG_RESET;
369 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
373 return CMD_RET_USAGE;
374 if (strcmp(argv[1], "0") == 0)
375 convert_flash_bank(BOOT_FROM_UPPER_BANK);
376 else if (strcmp(argv[1], "1") == 0)
377 convert_flash_bank(BOOT_FROM_LOWER_BANK);
379 return CMD_RET_USAGE;
385 boot_bank, 2, 0, flash_bank_cmd,
386 "Flash bank Selection Control",
387 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
390 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
393 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
396 return CMD_RET_USAGE;
397 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
398 cpld_data->system_rst = CONFIG_RESET;
399 else if (strcmp(argv[1], "init") == 0)
400 cpld_data->global_rst = INIT_RESET;
402 return CMD_RET_USAGE;
408 cpld_reset, 2, 0, cpld_reset_cmd,
411 " -reset with current CPLD configuration\n"
413 " -reset and initial CPLD configuration with default value"
417 static void convert_serdes_mux(int type, int need_reset)
420 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
422 current_serdes = cpld_data->serdes_mux;
426 current_serdes &= ~MASK_LANE_B;
429 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
432 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
435 current_serdes |= MASK_LANE_D;
438 current_serdes |= MASK_LANE_C;
440 case (LANED_PCIEX2 | LANEC_PCIEX1):
441 current_serdes |= MASK_LANE_C;
442 current_serdes &= ~MASK_LANE_D;
445 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
449 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
450 cpld_data->serdes_mux = current_serdes;
452 if (need_reset == 1) {
453 printf("Reset board to enable configuration\n");
454 cpld_data->system_rst = CONFIG_RESET;
458 void print_serdes_mux(void)
461 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
463 current_serdes = cpld_data->serdes_mux;
465 printf("Serdes Lane B: ");
466 if ((current_serdes & MASK_LANE_B) == 0)
469 printf("SGMII 1,\n");
471 printf("Serdes Lane C: ");
472 if ((current_serdes & MASK_LANE_C) == 0)
473 printf("SGMII 1,\n");
477 printf("Serdes Lane D: ");
478 if ((current_serdes & MASK_LANE_D) == 0)
481 printf("SGMII 2,\n");
483 printf("SGMII 1 is on lane ");
484 if ((current_serdes & MASK_SGMII) == 0)
490 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
494 return CMD_RET_USAGE;
495 if (strcmp(argv[1], "sata") == 0) {
496 printf("Set serdes lane B to SATA.\n");
497 convert_serdes_mux(LANEB_SATA, NEED_RESET);
498 } else if (strcmp(argv[1], "sgmii1b") == 0) {
499 printf("Set serdes lane B to SGMII 1.\n");
500 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
501 } else if (strcmp(argv[1], "sgmii1c") == 0) {
502 printf("Set serdes lane C to SGMII 1.\n");
503 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
504 } else if (strcmp(argv[1], "sgmii2") == 0) {
505 printf("Set serdes lane D to SGMII 2.\n");
506 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
507 } else if (strcmp(argv[1], "pciex1") == 0) {
508 printf("Set serdes lane C to PCIe X1.\n");
509 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
510 } else if (strcmp(argv[1], "pciex2") == 0) {
511 printf("Set serdes lane C & lane D to PCIe X2.\n");
512 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
513 } else if (strcmp(argv[1], "show") == 0) {
516 return CMD_RET_USAGE;
523 lane_bank, 2, 0, serdes_mux_cmd,
524 "Multiplexed function setting for SerDes Lanes",
526 " -change lane B to sata\n"
527 "lane_bank sgmii1b\n"
528 " -change lane B to SGMII1\n"
529 "lane_bank sgmii1c\n"
530 " -change lane C to SGMII1\n"
532 " -change lane D to SGMII2\n"
534 " -change lane C to PCIeX1\n"
536 " -change lane C & lane D to PCIeX2\n"
537 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"