board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <asm/arch/ls102xa_devdis.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <fsl_csu.h>
  18 #include <fsl_esdhc.h>
  19 #include <fsl_ifc.h>
  20 #include <fsl_immap.h>
  21 #include <netdev.h>
  22 #include <fsl_mdio.h>
  23 #include <tsec.h>
  24 #include <fsl_sec.h>
  25 #include <fsl_devdis.h>
  26 #include <spl.h>
  27 #include "../common/sleep.h"
  28 #ifdef CONFIG_U_QE
  29 #include "../../../drivers/qe/qe.h"
  30 #endif
  31
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define VERSION_MASK            0x00FF
  36 #define BANK_MASK               0x0001
  37 #define CONFIG_RESET            0x1
  38 #define INIT_RESET              0x1
  39
  40 #define CPLD_SET_MUX_SERDES     0x20
  41 #define CPLD_SET_BOOT_BANK      0x40
  42
  43 #define BOOT_FROM_UPPER_BANK    0x0
  44 #define BOOT_FROM_LOWER_BANK    0x1
  45
  46 #define LANEB_SATA              (0x01)
  47 #define LANEB_SGMII1            (0x02)
  48 #define LANEC_SGMII1            (0x04)
  49 #define LANEC_PCIEX1            (0x08)
  50 #define LANED_PCIEX2            (0x10)
  51 #define LANED_SGMII2            (0x20)
  52
  53 #define MASK_LANE_B             0x1
  54 #define MASK_LANE_C             0x2
  55 #define MASK_LANE_D             0x4
  56 #define MASK_SGMII              0x8
  57
  58 #define KEEP_STATUS             0x0
  59 #define NEED_RESET              0x1
  60
  61 #define SOFT_MUX_ON_I2C3_IFC    0x2
  62 #define SOFT_MUX_ON_CAN3_USB2   0x8
  63 #define SOFT_MUX_ON_QE_LCD      0x10
  64
  65 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  66 #define PIN_I2C3_IFC_MUX_IFC    0x1
  67 #define PIN_CAN3_USB2_MUX_USB2  0x0
  68 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  69 #define PIN_QE_LCD_MUX_LCD      0x0
  70 #define PIN_QE_LCD_MUX_QE       0x1
  71
  72 struct cpld_data {
  73         u8 cpld_ver;            /* cpld revision */
  74         u8 cpld_ver_sub;        /* cpld sub revision */
  75         u8 pcba_ver;            /* pcb revision number */
  76         u8 system_rst;          /* reset system by cpld */
  77         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  78         u8 cfg_rcw_src1;        /* Reset config word 1 */
  79         u8 cfg_rcw_src2;        /* Reset config word 2 */
  80         u8 vbank;               /* Flash bank selection Control */
  81         u8 gpio;                /* GPIO for TWR-ELEV */
  82         u8 i2c3_ifc_mux;
  83         u8 mux_spi2;
  84         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  85         u8 qe_lcd_mux;          /* QE and LCD Selection */
  86         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  87         u8 global_rst;          /* reset with init CPLD reg to default */
  88         u8 rev1;                /* Reserved */
  89         u8 rev2;                /* Reserved */
  90 };
  91
  92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  93 static void convert_serdes_mux(int type, int need_reset);
  94
  95 void cpld_show(void)
  96 {
  97         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  98
  99         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 100                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 101                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 102                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 103                in_8(&cpld_data->vbank) & BANK_MASK);
 104
 105 #ifdef CONFIG_DEBUG
 106         printf("soft_mux_on =%x\n",
 107                in_8(&cpld_data->soft_mux_on));
 108         printf("cfg_rcw_src1 =%x\n",
 109                in_8(&cpld_data->cfg_rcw_src1));
 110         printf("cfg_rcw_src2 =%x\n",
 111                in_8(&cpld_data->cfg_rcw_src2));
 112         printf("vbank =%x\n",
 113                in_8(&cpld_data->vbank));
 114         printf("gpio =%x\n",
 115                in_8(&cpld_data->gpio));
 116         printf("i2c3_ifc_mux =%x\n",
 117                in_8(&cpld_data->i2c3_ifc_mux));
 118         printf("mux_spi2 =%x\n",
 119                in_8(&cpld_data->mux_spi2));
 120         printf("can3_usb2_mux =%x\n",
 121                in_8(&cpld_data->can3_usb2_mux));
 122         printf("qe_lcd_mux =%x\n",
 123                in_8(&cpld_data->qe_lcd_mux));
 124         printf("serdes_mux =%x\n",
 125                in_8(&cpld_data->serdes_mux));
 126 #endif
 127 }
 128 #endif
 129
 130 int checkboard(void)
 131 {
 132         puts("Board: LS1021ATWR\n");
 133 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 134         cpld_show();
 135 #endif
 136
 137         return 0;
 138 }
 139
 140 unsigned int get_soc_major_rev(void)
 141 {
 142         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 143         unsigned int svr, major;
 144
 145         svr = in_be32(&gur->svr);
 146         major = SVR_MAJ(svr);
 147
 148         return major;
 149 }
 150
 151 void ddrmc_init(void)
 152 {
 153         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 154         u32 temp_sdram_cfg;
 155
 156         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 157
 158         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 159         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 160
 161         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 162         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 163         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 164         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 165         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 166         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 167
 168 #ifdef CONFIG_DEEP_SLEEP
 169         if (is_warm_boot()) {
 170                 out_be32(&ddr->sdram_cfg_2,
 171                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 172                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 173                 out_be32(&ddr->init_ext_addr, (1 << 31));
 174
 175                 /* DRAM VRef will not be trained */
 176                 out_be32(&ddr->ddr_cdr2,
 177                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 178         } else
 179 #endif
 180         {
 181                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 182                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 183         }
 184
 185         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 186         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 187
 188         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 189
 190         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 191
 192         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 193         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 194
 195         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 196
 197         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 198         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 199
 200         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 201         udelay(1);
 202
 203 #ifdef CONFIG_DEEP_SLEEP
 204         if (is_warm_boot()) {
 205                 /* enter self-refresh */
 206                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 207                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 208                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 209
 210                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 211         } else
 212 #endif
 213                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 214
 215         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 216
 217 #ifdef CONFIG_DEEP_SLEEP
 218         if (is_warm_boot()) {
 219                 /* exit self-refresh */
 220                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 221                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 222                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 223         }
 224 #endif
 225 }
 226
 227 int dram_init(void)
 228 {
 229 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 230         ddrmc_init();
 231 #endif
 232
 233         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 234
 235 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 236         fsl_dp_resume();
 237 #endif
 238
 239         return 0;
 240 }
 241
 242 #ifdef CONFIG_FSL_ESDHC
 243 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 244         {CONFIG_SYS_FSL_ESDHC_ADDR},
 245 };
 246
 247 int board_mmc_init(bd_t *bis)
 248 {
 249         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 250
 251         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 252 }
 253 #endif
 254
 255 #ifdef CONFIG_TSEC_ENET
 256 int board_eth_init(bd_t *bis)
 257 {
 258         struct fsl_pq_mdio_info mdio_info;
 259         struct tsec_info_struct tsec_info[4];
 260         int num = 0;
 261
 262 #ifdef CONFIG_TSEC1
 263         SET_STD_TSEC_INFO(tsec_info[num], 1);
 264         if (is_serdes_configured(SGMII_TSEC1)) {
 265                 puts("eTSEC1 is in sgmii mode.\n");
 266                 tsec_info[num].flags |= TSEC_SGMII;
 267         }
 268         num++;
 269 #endif
 270 #ifdef CONFIG_TSEC2
 271         SET_STD_TSEC_INFO(tsec_info[num], 2);
 272         if (is_serdes_configured(SGMII_TSEC2)) {
 273                 puts("eTSEC2 is in sgmii mode.\n");
 274                 tsec_info[num].flags |= TSEC_SGMII;
 275         }
 276         num++;
 277 #endif
 278 #ifdef CONFIG_TSEC3
 279         SET_STD_TSEC_INFO(tsec_info[num], 3);
 280         num++;
 281 #endif
 282         if (!num) {
 283                 printf("No TSECs initialized\n");
 284                 return 0;
 285         }
 286
 287         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 288         mdio_info.name = DEFAULT_MII_NAME;
 289         fsl_pq_mdio_init(bis, &mdio_info);
 290
 291         tsec_eth_init(bis, tsec_info, num);
 292
 293         return pci_eth_init(bis);
 294 }
 295 #endif
 296
 297 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 298 int config_serdes_mux(void)
 299 {
 300         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 301         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 302
 303         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 304         switch (protocol) {
 305         case 0x10:
 306                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 307                 convert_serdes_mux(LANED_PCIEX2 |
 308                                 LANEC_PCIEX1, KEEP_STATUS);
 309                 break;
 310         case 0x20:
 311                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 312                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 313                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 314                 break;
 315         case 0x30:
 316                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 317                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 318                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 319                 break;
 320         case 0x70:
 321                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 322                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 323                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 324                 break;
 325         }
 326
 327         return 0;
 328 }
 329 #endif
 330
 331 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 332 int config_board_mux(void)
 333 {
 334         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 335         int conflict_flag;
 336
 337         conflict_flag = 0;
 338         if (hwconfig("i2c3")) {
 339                 conflict_flag++;
 340                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 341                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 342         }
 343
 344         if (hwconfig("ifc")) {
 345                 conflict_flag++;
 346                 /* some signals can not enable simultaneous*/
 347                 if (conflict_flag > 1)
 348                         goto conflict;
 349                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 350                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 351         }
 352
 353         conflict_flag = 0;
 354         if (hwconfig("usb2")) {
 355                 conflict_flag++;
 356                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 357                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 358         }
 359
 360         if (hwconfig("can3")) {
 361                 conflict_flag++;
 362                 /* some signals can not enable simultaneous*/
 363                 if (conflict_flag > 1)
 364                         goto conflict;
 365                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 366                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 367         }
 368
 369         conflict_flag = 0;
 370         if (hwconfig("lcd")) {
 371                 conflict_flag++;
 372                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 373                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 374         }
 375
 376         if (hwconfig("qe")) {
 377                 conflict_flag++;
 378                 /* some signals can not enable simultaneous*/
 379                 if (conflict_flag > 1)
 380                         goto conflict;
 381                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 382                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 383         }
 384
 385         return 0;
 386
 387 conflict:
 388         printf("WARNING: pin conflict! MUX setting may failed!\n");
 389         return 0;
 390 }
 391 #endif
 392
 393 int board_early_init_f(void)
 394 {
 395         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 396         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 397         unsigned int major;
 398
 399 #ifdef CONFIG_TSEC_ENET
 400         /* clear BD & FR bits for BE BD's and frame data */
 401         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 402         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 403 #endif
 404
 405 #ifdef CONFIG_FSL_IFC
 406         init_early_memctl_regs();
 407 #endif
 408
 409 #ifdef CONFIG_FSL_DCU_FB
 410         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 411 #endif
 412
 413 #ifdef CONFIG_FSL_QSPI
 414         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 415 #endif
 416
 417         /* Configure Little endian for SAI, ASRC and SPDIF */
 418         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 419
 420         /*
 421          * Enable snoop requests and DVM message requests for
 422          * Slave insterface S4 (A7 core cluster)
 423          */
 424         out_le32(&cci->slave[4].snoop_ctrl,
 425                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 426
 427         major = get_soc_major_rev();
 428         if (major == SOC_MAJOR_VER_1_0) {
 429                 /*
 430                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 431                  * Register All transactions are treated as non-shareable
 432                  */
 433                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 434                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 435         }
 436
 437 #if defined(CONFIG_DEEP_SLEEP)
 438         if (is_warm_boot())
 439                 fsl_dp_disable_console();
 440 #endif
 441
 442         return 0;
 443 }
 444
 445 #ifdef CONFIG_SPL_BUILD
 446 void board_init_f(ulong dummy)
 447 {
 448         /* Clear the BSS */
 449         memset(__bss_start, 0, __bss_end - __bss_start);
 450
 451         get_clocks();
 452
 453 #if defined(CONFIG_DEEP_SLEEP)
 454         if (is_warm_boot())
 455                 fsl_dp_disable_console();
 456 #endif
 457
 458         preloader_console_init();
 459
 460         dram_init();
 461
 462         /* Allow OCRAM access permission as R/W */
 463 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 464         enable_layerscape_ns_access();
 465         enable_layerscape_ns_access();
 466 #endif
 467
 468         board_init_r(NULL, 0);
 469 }
 470 #endif
 471
 472
 473 struct liodn_id_table sec_liodn_tbl[] = {
 474         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 475         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 476         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 477         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 478         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 479         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 480         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 481         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 482         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 483         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 484         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 485         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 486         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 487         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 488         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 489         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 490 };
 491
 492 struct smmu_stream_id dev_stream_id[] = {
 493         { 0x100, 0x01, "ETSEC MAC1" },
 494         { 0x104, 0x02, "ETSEC MAC2" },
 495         { 0x108, 0x03, "ETSEC MAC3" },
 496         { 0x10c, 0x04, "PEX1" },
 497         { 0x110, 0x05, "PEX2" },
 498         { 0x114, 0x06, "qDMA" },
 499         { 0x118, 0x07, "SATA" },
 500         { 0x11c, 0x08, "USB3" },
 501         { 0x120, 0x09, "QE" },
 502         { 0x124, 0x0a, "eSDHC" },
 503         { 0x128, 0x0b, "eMA" },
 504         { 0x14c, 0x0c, "2D-ACE" },
 505         { 0x150, 0x0d, "USB2" },
 506         { 0x18c, 0x0e, "DEBUG" },
 507 };
 508
 509 #ifdef CONFIG_DEEP_SLEEP
 510 /* program the regulator (MC34VR500) to support deep sleep */
 511 void ls1twr_program_regulator(void)
 512 {
 513         unsigned int i2c_bus;
 514         u8 i2c_device_id;
 515
 516 #define LS1TWR_I2C_BUS_MC34VR500        1
 517 #define MC34VR500_ADDR                  0x8
 518 #define MC34VR500_DEVICEID              0x4
 519 #define MC34VR500_DEVICEID_MASK         0x0f
 520
 521         i2c_bus = i2c_get_bus_num();
 522         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 523         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 524                                         MC34VR500_DEVICEID_MASK;
 525         if (i2c_device_id != MC34VR500_DEVICEID) {
 526                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 527                 return;
 528         }
 529
 530         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 531         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 532         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 533         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 534         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 535
 536         i2c_set_bus_num(i2c_bus);
 537 }
 538 #endif
 539
 540 int board_init(void)
 541 {
 542 #ifndef CONFIG_SYS_FSL_NO_SERDES
 543         fsl_serdes_init();
 544 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 545         config_serdes_mux();
 546 #endif
 547 #endif
 548
 549         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 550                                       ARRAY_SIZE(sec_liodn_tbl));
 551         ls102xa_config_smmu_stream_id(dev_stream_id,
 552                                       ARRAY_SIZE(dev_stream_id));
 553
 554 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 555         enable_layerscape_ns_access();
 556 #endif
 557
 558 #ifdef CONFIG_U_QE
 559         u_qe_init();
 560 #endif
 561
 562 #ifdef CONFIG_DEEP_SLEEP
 563         ls1twr_program_regulator();
 564 #endif
 565         return 0;
 566 }
 567
 568 #if defined(CONFIG_MISC_INIT_R)
 569 int misc_init_r(void)
 570 {
 571 #ifdef CONFIG_FSL_DEVICE_DISABLE
 572         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 573 #endif
 574 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 575         config_board_mux();
 576 #endif
 577
 578 #ifdef CONFIG_FSL_CAAM
 579         return sec_init();
 580 #endif
 581 }
 582 #endif
 583
 584 #if defined(CONFIG_DEEP_SLEEP)
 585 void board_sleep_prepare(void)
 586 {
 587 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 588         enable_layerscape_ns_access();
 589 #endif
 590 }
 591 #endif
 592
 593 int ft_board_setup(void *blob, bd_t *bd)
 594 {
 595         ft_cpu_setup(blob, bd);
 596
 597 #ifdef CONFIG_PCI
 598         ft_pci_setup(blob, bd);
 599 #endif
 600
 601         return 0;
 602 }
 603
 604 u8 flash_read8(void *addr)
 605 {
 606         return __raw_readb(addr + 1);
 607 }
 608
 609 void flash_write16(u16 val, void *addr)
 610 {
 611         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 612
 613         __raw_writew(shftval, addr);
 614 }
 615
 616 u16 flash_read16(void *addr)
 617 {
 618         u16 val = __raw_readw(addr);
 619
 620         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 621 }
 622
 623 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 624 static void convert_flash_bank(char bank)
 625 {
 626         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 627
 628         printf("Now switch to boot from flash bank %d.\n", bank);
 629         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 630         cpld_data->vbank = bank;
 631
 632         printf("Reset board to enable configuration.\n");
 633         cpld_data->system_rst = CONFIG_RESET;
 634 }
 635
 636 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 637                           char * const argv[])
 638 {
 639         if (argc != 2)
 640                 return CMD_RET_USAGE;
 641         if (strcmp(argv[1], "0") == 0)
 642                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 643         else if (strcmp(argv[1], "1") == 0)
 644                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 645         else
 646                 return CMD_RET_USAGE;
 647
 648         return 0;
 649 }
 650
 651 U_BOOT_CMD(
 652         boot_bank, 2, 0, flash_bank_cmd,
 653         "Flash bank Selection Control",
 654         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 655 );
 656
 657 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 658                           char * const argv[])
 659 {
 660         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 661
 662         if (argc > 2)
 663                 return CMD_RET_USAGE;
 664         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 665                 cpld_data->system_rst = CONFIG_RESET;
 666         else if (strcmp(argv[1], "init") == 0)
 667                 cpld_data->global_rst = INIT_RESET;
 668         else
 669                 return CMD_RET_USAGE;
 670
 671         return 0;
 672 }
 673
 674 U_BOOT_CMD(
 675         cpld_reset, 2, 0, cpld_reset_cmd,
 676         "Reset via CPLD",
 677         "conf\n"
 678         "       -reset with current CPLD configuration\n"
 679         "init\n"
 680         "       -reset and initial CPLD configuration with default value"
 681
 682 );
 683
 684 static void convert_serdes_mux(int type, int need_reset)
 685 {
 686         char current_serdes;
 687         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 688
 689         current_serdes = cpld_data->serdes_mux;
 690
 691         switch (type) {
 692         case LANEB_SATA:
 693                 current_serdes &= ~MASK_LANE_B;
 694                 break;
 695         case LANEB_SGMII1:
 696                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 697                 break;
 698         case LANEC_SGMII1:
 699                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 700                 break;
 701         case LANED_SGMII2:
 702                 current_serdes |= MASK_LANE_D;
 703                 break;
 704         case LANEC_PCIEX1:
 705                 current_serdes |= MASK_LANE_C;
 706                 break;
 707         case (LANED_PCIEX2 | LANEC_PCIEX1):
 708                 current_serdes |= MASK_LANE_C;
 709                 current_serdes &= ~MASK_LANE_D;
 710                 break;
 711         default:
 712                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 713                 return;
 714         }
 715
 716         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 717         cpld_data->serdes_mux = current_serdes;
 718
 719         if (need_reset == 1) {
 720                 printf("Reset board to enable configuration\n");
 721                 cpld_data->system_rst = CONFIG_RESET;
 722         }
 723 }
 724
 725 void print_serdes_mux(void)
 726 {
 727         char current_serdes;
 728         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 729
 730         current_serdes = cpld_data->serdes_mux;
 731
 732         printf("Serdes Lane B: ");
 733         if ((current_serdes & MASK_LANE_B) == 0)
 734                 printf("SATA,\n");
 735         else
 736                 printf("SGMII 1,\n");
 737
 738         printf("Serdes Lane C: ");
 739         if ((current_serdes & MASK_LANE_C) == 0)
 740                 printf("SGMII 1,\n");
 741         else
 742                 printf("PCIe,\n");
 743
 744         printf("Serdes Lane D: ");
 745         if ((current_serdes & MASK_LANE_D) == 0)
 746                 printf("PCIe,\n");
 747         else
 748                 printf("SGMII 2,\n");
 749
 750         printf("SGMII 1 is on lane ");
 751         if ((current_serdes & MASK_SGMII) == 0)
 752                 printf("C.\n");
 753         else
 754                 printf("B.\n");
 755 }
 756
 757 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 758                           char * const argv[])
 759 {
 760         if (argc != 2)
 761                 return CMD_RET_USAGE;
 762         if (strcmp(argv[1], "sata") == 0) {
 763                 printf("Set serdes lane B to SATA.\n");
 764                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 765         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 766                 printf("Set serdes lane B to SGMII 1.\n");
 767                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 768         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 769                 printf("Set serdes lane C to SGMII 1.\n");
 770                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 771         } else if (strcmp(argv[1], "sgmii2") == 0) {
 772                 printf("Set serdes lane D to SGMII 2.\n");
 773                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 774         } else if (strcmp(argv[1], "pciex1") == 0) {
 775                 printf("Set serdes lane C to PCIe X1.\n");
 776                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 777         } else if (strcmp(argv[1], "pciex2") == 0) {
 778                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 779                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 780         } else if (strcmp(argv[1], "show") == 0) {
 781                 print_serdes_mux();
 782         } else {
 783                 return CMD_RET_USAGE;
 784         }
 785
 786         return 0;
 787 }
 788
 789 U_BOOT_CMD(
 790         lane_bank, 2, 0, serdes_mux_cmd,
 791         "Multiplexed function setting for SerDes Lanes",
 792         "sata\n"
 793         "       -change lane B to sata\n"
 794         "lane_bank sgmii1b\n"
 795         "       -change lane B to SGMII1\n"
 796         "lane_bank sgmii1c\n"
 797         "       -change lane C to SGMII1\n"
 798         "lane_bank sgmii2\n"
 799         "       -change lane D to SGMII2\n"
 800         "lane_bank pciex1\n"
 801         "       -change lane C to PCIeX1\n"
 802         "lane_bank pciex2\n"
 803         "       -change lane C & lane D to PCIeX2\n"
 804         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 805 );
 806 #endif