1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
19 #include <fsl_immap.h>
24 #include <fsl_devdis.h>
26 #include "../common/sleep.h"
30 #include <fsl_validate.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define VERSION_MASK 0x00FF
36 #define BANK_MASK 0x0001
37 #define CONFIG_RESET 0x1
38 #define INIT_RESET 0x1
40 #define CPLD_SET_MUX_SERDES 0x20
41 #define CPLD_SET_BOOT_BANK 0x40
43 #define BOOT_FROM_UPPER_BANK 0x0
44 #define BOOT_FROM_LOWER_BANK 0x1
46 #define LANEB_SATA (0x01)
47 #define LANEB_SGMII1 (0x02)
48 #define LANEC_SGMII1 (0x04)
49 #define LANEC_PCIEX1 (0x08)
50 #define LANED_PCIEX2 (0x10)
51 #define LANED_SGMII2 (0x20)
53 #define MASK_LANE_B 0x1
54 #define MASK_LANE_C 0x2
55 #define MASK_LANE_D 0x4
56 #define MASK_SGMII 0x8
58 #define KEEP_STATUS 0x0
59 #define NEED_RESET 0x1
61 #define SOFT_MUX_ON_I2C3_IFC 0x2
62 #define SOFT_MUX_ON_CAN3_USB2 0x8
63 #define SOFT_MUX_ON_QE_LCD 0x10
65 #define PIN_I2C3_IFC_MUX_I2C3 0x0
66 #define PIN_I2C3_IFC_MUX_IFC 0x1
67 #define PIN_CAN3_USB2_MUX_USB2 0x0
68 #define PIN_CAN3_USB2_MUX_CAN3 0x1
69 #define PIN_QE_LCD_MUX_LCD 0x0
70 #define PIN_QE_LCD_MUX_QE 0x1
73 u8 cpld_ver; /* cpld revision */
74 u8 cpld_ver_sub; /* cpld sub revision */
75 u8 pcba_ver; /* pcb revision number */
76 u8 system_rst; /* reset system by cpld */
77 u8 soft_mux_on; /* CPLD override physical switches Enable */
78 u8 cfg_rcw_src1; /* Reset config word 1 */
79 u8 cfg_rcw_src2; /* Reset config word 2 */
80 u8 vbank; /* Flash bank selection Control */
81 u8 gpio; /* GPIO for TWR-ELEV */
84 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
85 u8 qe_lcd_mux; /* QE and LCD Selection */
86 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
87 u8 global_rst; /* reset with init CPLD reg to default */
88 u8 rev1; /* Reserved */
89 u8 rev2; /* Reserved */
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
93 static void cpld_show(void)
95 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
97 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
98 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
99 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
100 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
101 in_8(&cpld_data->vbank) & BANK_MASK);
104 printf("soft_mux_on =%x\n",
105 in_8(&cpld_data->soft_mux_on));
106 printf("cfg_rcw_src1 =%x\n",
107 in_8(&cpld_data->cfg_rcw_src1));
108 printf("cfg_rcw_src2 =%x\n",
109 in_8(&cpld_data->cfg_rcw_src2));
110 printf("vbank =%x\n",
111 in_8(&cpld_data->vbank));
113 in_8(&cpld_data->gpio));
114 printf("i2c3_ifc_mux =%x\n",
115 in_8(&cpld_data->i2c3_ifc_mux));
116 printf("mux_spi2 =%x\n",
117 in_8(&cpld_data->mux_spi2));
118 printf("can3_usb2_mux =%x\n",
119 in_8(&cpld_data->can3_usb2_mux));
120 printf("qe_lcd_mux =%x\n",
121 in_8(&cpld_data->qe_lcd_mux));
122 printf("serdes_mux =%x\n",
123 in_8(&cpld_data->serdes_mux));
130 puts("Board: LS1021ATWR\n");
131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
138 void ddrmc_init(void)
140 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
141 u32 temp_sdram_cfg, tmp;
143 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
145 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
146 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
148 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
149 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
150 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
151 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
152 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
153 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
155 #ifdef CONFIG_DEEP_SLEEP
156 if (is_warm_boot()) {
157 out_be32(&ddr->sdram_cfg_2,
158 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
159 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
160 out_be32(&ddr->init_ext_addr, (1 << 31));
162 /* DRAM VRef will not be trained */
163 out_be32(&ddr->ddr_cdr2,
164 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
168 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
169 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
172 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
173 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
175 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
177 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
179 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
180 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
182 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
184 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
185 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
187 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
189 /* DDR erratum A-009942 */
190 tmp = in_be32(&ddr->debug[28]);
191 out_be32(&ddr->debug[28], tmp | 0x0070006f);
195 #ifdef CONFIG_DEEP_SLEEP
196 if (is_warm_boot()) {
197 /* enter self-refresh */
198 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
199 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
200 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
202 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
205 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
207 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
209 #ifdef CONFIG_DEEP_SLEEP
210 if (is_warm_boot()) {
211 /* exit self-refresh */
212 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
213 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
214 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
221 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
225 erratum_a008850_post();
227 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
229 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
236 int board_eth_init(bd_t *bis)
238 return pci_eth_init(bis);
241 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
242 static void convert_serdes_mux(int type, int need_reset)
245 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
247 current_serdes = cpld_data->serdes_mux;
251 current_serdes &= ~MASK_LANE_B;
254 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
257 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
260 current_serdes |= MASK_LANE_D;
263 current_serdes |= MASK_LANE_C;
265 case (LANED_PCIEX2 | LANEC_PCIEX1):
266 current_serdes |= MASK_LANE_C;
267 current_serdes &= ~MASK_LANE_D;
270 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
274 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
275 cpld_data->serdes_mux = current_serdes;
277 if (need_reset == 1) {
278 printf("Reset board to enable configuration\n");
279 cpld_data->system_rst = CONFIG_RESET;
283 int config_serdes_mux(void)
285 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
286 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
288 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
291 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
292 convert_serdes_mux(LANED_PCIEX2 |
293 LANEC_PCIEX1, KEEP_STATUS);
296 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
297 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
298 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
301 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
302 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
303 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
306 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
307 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
308 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
316 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
317 int config_board_mux(void)
319 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
323 if (hwconfig("i2c3")) {
325 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
326 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
329 if (hwconfig("ifc")) {
331 /* some signals can not enable simultaneous*/
332 if (conflict_flag > 1)
334 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
335 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
339 if (hwconfig("usb2")) {
341 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
342 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
345 if (hwconfig("can3")) {
347 /* some signals can not enable simultaneous*/
348 if (conflict_flag > 1)
350 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
351 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
355 if (hwconfig("lcd")) {
357 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
358 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
361 if (hwconfig("qe")) {
363 /* some signals can not enable simultaneous*/
364 if (conflict_flag > 1)
366 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
367 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
373 printf("WARNING: pin conflict! MUX setting may failed!\n");
378 int board_early_init_f(void)
380 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
382 #ifdef CONFIG_TSEC_ENET
383 /* clear BD & FR bits for BE BD's and frame data */
384 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
385 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
388 #ifdef CONFIG_FSL_IFC
389 init_early_memctl_regs();
394 #if defined(CONFIG_DEEP_SLEEP)
395 if (is_warm_boot()) {
404 #ifdef CONFIG_SPL_BUILD
405 void board_init_f(ulong dummy)
407 void (*second_uboot)(void);
410 memset(__bss_start, 0, __bss_end - __bss_start);
414 #if defined(CONFIG_DEEP_SLEEP)
416 fsl_dp_disable_console();
419 preloader_console_init();
424 /* Allow OCRAM access permission as R/W */
425 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
426 enable_layerscape_ns_access();
430 * if it is woken up from deep sleep, then jump to second
431 * stage uboot and continue executing without recopying
432 * it from SD since it has already been reserved in memeory
435 if (is_warm_boot()) {
436 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
440 board_init_r(NULL, 0);
444 #ifdef CONFIG_DEEP_SLEEP
445 /* program the regulator (MC34VR500) to support deep sleep */
446 void ls1twr_program_regulator(void)
448 unsigned int i2c_bus;
451 #define LS1TWR_I2C_BUS_MC34VR500 1
452 #define MC34VR500_ADDR 0x8
453 #define MC34VR500_DEVICEID 0x4
454 #define MC34VR500_DEVICEID_MASK 0x0f
456 i2c_bus = i2c_get_bus_num();
457 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
458 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
459 MC34VR500_DEVICEID_MASK;
460 if (i2c_device_id != MC34VR500_DEVICEID) {
461 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
465 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
466 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
467 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
468 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
469 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
471 i2c_set_bus_num(i2c_bus);
477 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
481 #ifndef CONFIG_SYS_FSL_NO_SERDES
483 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
488 ls102xa_smmu_stream_id_init();
494 #ifdef CONFIG_DEEP_SLEEP
495 ls1twr_program_regulator();
500 #if defined(CONFIG_SPL_BUILD)
501 void spl_board_init(void)
503 ls102xa_smmu_stream_id_init();
507 #ifdef CONFIG_BOARD_LATE_INIT
508 int board_late_init(void)
510 #ifdef CONFIG_CHAIN_OF_TRUST
511 fsl_setenv_chain_of_trust();
518 #if defined(CONFIG_MISC_INIT_R)
519 int misc_init_r(void)
521 #ifdef CONFIG_FSL_DEVICE_DISABLE
522 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
524 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
528 #ifdef CONFIG_FSL_CAAM
534 #if defined(CONFIG_DEEP_SLEEP)
535 void board_sleep_prepare(void)
537 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
538 enable_layerscape_ns_access();
543 int ft_board_setup(void *blob, bd_t *bd)
545 ft_cpu_setup(blob, bd);
548 ft_pci_setup(blob, bd);
554 u8 flash_read8(void *addr)
556 return __raw_readb(addr + 1);
559 void flash_write16(u16 val, void *addr)
561 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
563 __raw_writew(shftval, addr);
566 u16 flash_read16(void *addr)
568 u16 val = __raw_readw(addr);
570 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
573 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
574 && !defined(CONFIG_SPL_BUILD)
575 static void convert_flash_bank(char bank)
577 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
579 printf("Now switch to boot from flash bank %d.\n", bank);
580 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
581 cpld_data->vbank = bank;
583 printf("Reset board to enable configuration.\n");
584 cpld_data->system_rst = CONFIG_RESET;
587 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
591 return CMD_RET_USAGE;
592 if (strcmp(argv[1], "0") == 0)
593 convert_flash_bank(BOOT_FROM_UPPER_BANK);
594 else if (strcmp(argv[1], "1") == 0)
595 convert_flash_bank(BOOT_FROM_LOWER_BANK);
597 return CMD_RET_USAGE;
603 boot_bank, 2, 0, flash_bank_cmd,
604 "Flash bank Selection Control",
605 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
608 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
611 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
614 return CMD_RET_USAGE;
615 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
616 cpld_data->system_rst = CONFIG_RESET;
617 else if (strcmp(argv[1], "init") == 0)
618 cpld_data->global_rst = INIT_RESET;
620 return CMD_RET_USAGE;
626 cpld_reset, 2, 0, cpld_reset_cmd,
629 " -reset with current CPLD configuration\n"
631 " -reset and initial CPLD configuration with default value"
635 static void print_serdes_mux(void)
638 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
640 current_serdes = cpld_data->serdes_mux;
642 printf("Serdes Lane B: ");
643 if ((current_serdes & MASK_LANE_B) == 0)
646 printf("SGMII 1,\n");
648 printf("Serdes Lane C: ");
649 if ((current_serdes & MASK_LANE_C) == 0)
650 printf("SGMII 1,\n");
654 printf("Serdes Lane D: ");
655 if ((current_serdes & MASK_LANE_D) == 0)
658 printf("SGMII 2,\n");
660 printf("SGMII 1 is on lane ");
661 if ((current_serdes & MASK_SGMII) == 0)
667 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
671 return CMD_RET_USAGE;
672 if (strcmp(argv[1], "sata") == 0) {
673 printf("Set serdes lane B to SATA.\n");
674 convert_serdes_mux(LANEB_SATA, NEED_RESET);
675 } else if (strcmp(argv[1], "sgmii1b") == 0) {
676 printf("Set serdes lane B to SGMII 1.\n");
677 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
678 } else if (strcmp(argv[1], "sgmii1c") == 0) {
679 printf("Set serdes lane C to SGMII 1.\n");
680 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
681 } else if (strcmp(argv[1], "sgmii2") == 0) {
682 printf("Set serdes lane D to SGMII 2.\n");
683 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
684 } else if (strcmp(argv[1], "pciex1") == 0) {
685 printf("Set serdes lane C to PCIe X1.\n");
686 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
687 } else if (strcmp(argv[1], "pciex2") == 0) {
688 printf("Set serdes lane C & lane D to PCIe X2.\n");
689 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
690 } else if (strcmp(argv[1], "show") == 0) {
693 return CMD_RET_USAGE;
700 lane_bank, 2, 0, serdes_mux_cmd,
701 "Multiplexed function setting for SerDes Lanes",
703 " -change lane B to sata\n"
704 "lane_bank sgmii1b\n"
705 " -change lane B to SGMII1\n"
706 "lane_bank sgmii1c\n"
707 " -change lane C to SGMII1\n"
709 " -change lane D to SGMII2\n"
711 " -change lane C to PCIeX1\n"
713 " -change lane C & lane D to PCIeX2\n"
714 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"