board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ls102xa_devdis.h>
  14 #include <asm/arch/ls102xa_soc.h>
  15 #include <asm/arch/ls102xa_sata.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_csu.h>
  19 #include <fsl_esdhc.h>
  20 #include <fsl_ifc.h>
  21 #include <fsl_immap.h>
  22 #include <netdev.h>
  23 #include <fsl_mdio.h>
  24 #include <tsec.h>
  25 #include <fsl_sec.h>
  26 #include <fsl_devdis.h>
  27 #include <spl.h>
  28 #include "../common/sleep.h"
  29 #ifdef CONFIG_U_QE
  30 #include <fsl_qe.h>
  31 #endif
  32 #include <fsl_validate.h>
  33
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define VERSION_MASK            0x00FF
  38 #define BANK_MASK               0x0001
  39 #define CONFIG_RESET            0x1
  40 #define INIT_RESET              0x1
  41
  42 #define CPLD_SET_MUX_SERDES     0x20
  43 #define CPLD_SET_BOOT_BANK      0x40
  44
  45 #define BOOT_FROM_UPPER_BANK    0x0
  46 #define BOOT_FROM_LOWER_BANK    0x1
  47
  48 #define LANEB_SATA              (0x01)
  49 #define LANEB_SGMII1            (0x02)
  50 #define LANEC_SGMII1            (0x04)
  51 #define LANEC_PCIEX1            (0x08)
  52 #define LANED_PCIEX2            (0x10)
  53 #define LANED_SGMII2            (0x20)
  54
  55 #define MASK_LANE_B             0x1
  56 #define MASK_LANE_C             0x2
  57 #define MASK_LANE_D             0x4
  58 #define MASK_SGMII              0x8
  59
  60 #define KEEP_STATUS             0x0
  61 #define NEED_RESET              0x1
  62
  63 #define SOFT_MUX_ON_I2C3_IFC    0x2
  64 #define SOFT_MUX_ON_CAN3_USB2   0x8
  65 #define SOFT_MUX_ON_QE_LCD      0x10
  66
  67 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  68 #define PIN_I2C3_IFC_MUX_IFC    0x1
  69 #define PIN_CAN3_USB2_MUX_USB2  0x0
  70 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  71 #define PIN_QE_LCD_MUX_LCD      0x0
  72 #define PIN_QE_LCD_MUX_QE       0x1
  73
  74 struct cpld_data {
  75         u8 cpld_ver;            /* cpld revision */
  76         u8 cpld_ver_sub;        /* cpld sub revision */
  77         u8 pcba_ver;            /* pcb revision number */
  78         u8 system_rst;          /* reset system by cpld */
  79         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  80         u8 cfg_rcw_src1;        /* Reset config word 1 */
  81         u8 cfg_rcw_src2;        /* Reset config word 2 */
  82         u8 vbank;               /* Flash bank selection Control */
  83         u8 gpio;                /* GPIO for TWR-ELEV */
  84         u8 i2c3_ifc_mux;
  85         u8 mux_spi2;
  86         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  87         u8 qe_lcd_mux;          /* QE and LCD Selection */
  88         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  89         u8 global_rst;          /* reset with init CPLD reg to default */
  90         u8 rev1;                /* Reserved */
  91         u8 rev2;                /* Reserved */
  92 };
  93
  94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  95 static void convert_serdes_mux(int type, int need_reset);
  96
  97 void cpld_show(void)
  98 {
  99         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 100
 101         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 102                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 103                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 104                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 105                in_8(&cpld_data->vbank) & BANK_MASK);
 106
 107 #ifdef CONFIG_DEBUG
 108         printf("soft_mux_on =%x\n",
 109                in_8(&cpld_data->soft_mux_on));
 110         printf("cfg_rcw_src1 =%x\n",
 111                in_8(&cpld_data->cfg_rcw_src1));
 112         printf("cfg_rcw_src2 =%x\n",
 113                in_8(&cpld_data->cfg_rcw_src2));
 114         printf("vbank =%x\n",
 115                in_8(&cpld_data->vbank));
 116         printf("gpio =%x\n",
 117                in_8(&cpld_data->gpio));
 118         printf("i2c3_ifc_mux =%x\n",
 119                in_8(&cpld_data->i2c3_ifc_mux));
 120         printf("mux_spi2 =%x\n",
 121                in_8(&cpld_data->mux_spi2));
 122         printf("can3_usb2_mux =%x\n",
 123                in_8(&cpld_data->can3_usb2_mux));
 124         printf("qe_lcd_mux =%x\n",
 125                in_8(&cpld_data->qe_lcd_mux));
 126         printf("serdes_mux =%x\n",
 127                in_8(&cpld_data->serdes_mux));
 128 #endif
 129 }
 130 #endif
 131
 132 int checkboard(void)
 133 {
 134         puts("Board: LS1021ATWR\n");
 135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 136         cpld_show();
 137 #endif
 138
 139         return 0;
 140 }
 141
 142 void ddrmc_init(void)
 143 {
 144         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 145         u32 temp_sdram_cfg;
 146
 147         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 148
 149         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 150         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 151
 152         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 153         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 154         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 155         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 156         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 157         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 158
 159 #ifdef CONFIG_DEEP_SLEEP
 160         if (is_warm_boot()) {
 161                 out_be32(&ddr->sdram_cfg_2,
 162                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 163                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 164                 out_be32(&ddr->init_ext_addr, (1 << 31));
 165
 166                 /* DRAM VRef will not be trained */
 167                 out_be32(&ddr->ddr_cdr2,
 168                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 169         } else
 170 #endif
 171         {
 172                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 173                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 174         }
 175
 176         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 177         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 178
 179         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 180
 181         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 182
 183         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 184         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 185
 186         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 187
 188         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 189         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 190
 191         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 192         udelay(1);
 193
 194 #ifdef CONFIG_DEEP_SLEEP
 195         if (is_warm_boot()) {
 196                 /* enter self-refresh */
 197                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 198                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 199                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 200
 201                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 202         } else
 203 #endif
 204                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 205
 206         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 207
 208 #ifdef CONFIG_DEEP_SLEEP
 209         if (is_warm_boot()) {
 210                 /* exit self-refresh */
 211                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 212                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 213                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 214         }
 215 #endif
 216 }
 217
 218 int dram_init(void)
 219 {
 220 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 221         ddrmc_init();
 222 #endif
 223
 224         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 225
 226 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 227         fsl_dp_resume();
 228 #endif
 229
 230         return 0;
 231 }
 232
 233 #ifdef CONFIG_FSL_ESDHC
 234 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 235         {CONFIG_SYS_FSL_ESDHC_ADDR},
 236 };
 237
 238 int board_mmc_init(bd_t *bis)
 239 {
 240         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 241
 242         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 243 }
 244 #endif
 245
 246 int board_eth_init(bd_t *bis)
 247 {
 248 #ifdef CONFIG_TSEC_ENET
 249         struct fsl_pq_mdio_info mdio_info;
 250         struct tsec_info_struct tsec_info[4];
 251         int num = 0;
 252
 253 #ifdef CONFIG_TSEC1
 254         SET_STD_TSEC_INFO(tsec_info[num], 1);
 255         if (is_serdes_configured(SGMII_TSEC1)) {
 256                 puts("eTSEC1 is in sgmii mode.\n");
 257                 tsec_info[num].flags |= TSEC_SGMII;
 258         }
 259         num++;
 260 #endif
 261 #ifdef CONFIG_TSEC2
 262         SET_STD_TSEC_INFO(tsec_info[num], 2);
 263         if (is_serdes_configured(SGMII_TSEC2)) {
 264                 puts("eTSEC2 is in sgmii mode.\n");
 265                 tsec_info[num].flags |= TSEC_SGMII;
 266         }
 267         num++;
 268 #endif
 269 #ifdef CONFIG_TSEC3
 270         SET_STD_TSEC_INFO(tsec_info[num], 3);
 271         num++;
 272 #endif
 273         if (!num) {
 274                 printf("No TSECs initialized\n");
 275                 return 0;
 276         }
 277
 278         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 279         mdio_info.name = DEFAULT_MII_NAME;
 280         fsl_pq_mdio_init(bis, &mdio_info);
 281
 282         tsec_eth_init(bis, tsec_info, num);
 283 #endif
 284
 285         return pci_eth_init(bis);
 286 }
 287
 288 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 289 int config_serdes_mux(void)
 290 {
 291         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 292         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 293
 294         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 295         switch (protocol) {
 296         case 0x10:
 297                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 298                 convert_serdes_mux(LANED_PCIEX2 |
 299                                 LANEC_PCIEX1, KEEP_STATUS);
 300                 break;
 301         case 0x20:
 302                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 303                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 304                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 305                 break;
 306         case 0x30:
 307                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 308                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 309                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 310                 break;
 311         case 0x70:
 312                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 313                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 314                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320 #endif
 321
 322 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 323 int config_board_mux(void)
 324 {
 325         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 326         int conflict_flag;
 327
 328         conflict_flag = 0;
 329         if (hwconfig("i2c3")) {
 330                 conflict_flag++;
 331                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 332                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 333         }
 334
 335         if (hwconfig("ifc")) {
 336                 conflict_flag++;
 337                 /* some signals can not enable simultaneous*/
 338                 if (conflict_flag > 1)
 339                         goto conflict;
 340                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 341                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 342         }
 343
 344         conflict_flag = 0;
 345         if (hwconfig("usb2")) {
 346                 conflict_flag++;
 347                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 348                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 349         }
 350
 351         if (hwconfig("can3")) {
 352                 conflict_flag++;
 353                 /* some signals can not enable simultaneous*/
 354                 if (conflict_flag > 1)
 355                         goto conflict;
 356                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 357                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 358         }
 359
 360         conflict_flag = 0;
 361         if (hwconfig("lcd")) {
 362                 conflict_flag++;
 363                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 364                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 365         }
 366
 367         if (hwconfig("qe")) {
 368                 conflict_flag++;
 369                 /* some signals can not enable simultaneous*/
 370                 if (conflict_flag > 1)
 371                         goto conflict;
 372                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 373                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 374         }
 375
 376         return 0;
 377
 378 conflict:
 379         printf("WARNING: pin conflict! MUX setting may failed!\n");
 380         return 0;
 381 }
 382 #endif
 383
 384 int board_early_init_f(void)
 385 {
 386         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 387
 388 #ifdef CONFIG_TSEC_ENET
 389         /* clear BD & FR bits for BE BD's and frame data */
 390         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 391         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 392 #endif
 393
 394 #ifdef CONFIG_FSL_IFC
 395         init_early_memctl_regs();
 396 #endif
 397
 398         arch_soc_init();
 399
 400 #if defined(CONFIG_DEEP_SLEEP)
 401         if (is_warm_boot()) {
 402                 timer_init();
 403                 dram_init();
 404         }
 405 #endif
 406
 407         return 0;
 408 }
 409
 410 #ifdef CONFIG_SPL_BUILD
 411 void board_init_f(ulong dummy)
 412 {
 413         void (*second_uboot)(void);
 414
 415         /* Clear the BSS */
 416         memset(__bss_start, 0, __bss_end - __bss_start);
 417
 418         get_clocks();
 419
 420 #if defined(CONFIG_DEEP_SLEEP)
 421         if (is_warm_boot())
 422                 fsl_dp_disable_console();
 423 #endif
 424
 425         preloader_console_init();
 426
 427         dram_init();
 428
 429         /* Allow OCRAM access permission as R/W */
 430 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 431         enable_layerscape_ns_access();
 432         enable_layerscape_ns_access();
 433 #endif
 434
 435         /*
 436          * if it is woken up from deep sleep, then jump to second
 437          * stage uboot and continue executing without recopying
 438          * it from SD since it has already been reserved in memeory
 439          * in last boot.
 440          */
 441         if (is_warm_boot()) {
 442                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 443                 second_uboot();
 444         }
 445
 446         board_init_r(NULL, 0);
 447 }
 448 #endif
 449
 450 #ifdef CONFIG_DEEP_SLEEP
 451 /* program the regulator (MC34VR500) to support deep sleep */
 452 void ls1twr_program_regulator(void)
 453 {
 454         unsigned int i2c_bus;
 455         u8 i2c_device_id;
 456
 457 #define LS1TWR_I2C_BUS_MC34VR500        1
 458 #define MC34VR500_ADDR                  0x8
 459 #define MC34VR500_DEVICEID              0x4
 460 #define MC34VR500_DEVICEID_MASK         0x0f
 461
 462         i2c_bus = i2c_get_bus_num();
 463         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 464         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 465                                         MC34VR500_DEVICEID_MASK;
 466         if (i2c_device_id != MC34VR500_DEVICEID) {
 467                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 468                 return;
 469         }
 470
 471         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 472         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 473         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 474         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 475         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 476
 477         i2c_set_bus_num(i2c_bus);
 478 }
 479 #endif
 480
 481 int board_init(void)
 482 {
 483 #ifndef CONFIG_SYS_FSL_NO_SERDES
 484         fsl_serdes_init();
 485 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 486         config_serdes_mux();
 487 #endif
 488 #endif
 489
 490         ls102xa_smmu_stream_id_init();
 491
 492 #ifdef CONFIG_U_QE
 493         u_qe_init();
 494 #endif
 495
 496 #ifdef CONFIG_DEEP_SLEEP
 497         ls1twr_program_regulator();
 498 #endif
 499         return 0;
 500 }
 501
 502 #if defined(CONFIG_SPL_BUILD)
 503 void spl_board_init(void)
 504 {
 505         ls102xa_smmu_stream_id_init();
 506 }
 507 #endif
 508
 509 #ifdef CONFIG_BOARD_LATE_INIT
 510 int board_late_init(void)
 511 {
 512 #ifdef CONFIG_SCSI_AHCI_PLAT
 513         ls1021a_sata_init();
 514 #endif
 515 #ifdef CONFIG_CHAIN_OF_TRUST
 516         fsl_setenv_chain_of_trust();
 517 #endif
 518
 519         return 0;
 520 }
 521 #endif
 522
 523 #if defined(CONFIG_MISC_INIT_R)
 524 int misc_init_r(void)
 525 {
 526 #ifdef CONFIG_FSL_DEVICE_DISABLE
 527         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 528 #endif
 529 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 530         config_board_mux();
 531 #endif
 532
 533 #ifdef CONFIG_FSL_CAAM
 534         return sec_init();
 535 #endif
 536 }
 537 #endif
 538
 539 #if defined(CONFIG_DEEP_SLEEP)
 540 void board_sleep_prepare(void)
 541 {
 542 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 543         enable_layerscape_ns_access();
 544 #endif
 545 }
 546 #endif
 547
 548 int ft_board_setup(void *blob, bd_t *bd)
 549 {
 550         ft_cpu_setup(blob, bd);
 551
 552 #ifdef CONFIG_PCI
 553         ft_pci_setup(blob, bd);
 554 #endif
 555
 556         return 0;
 557 }
 558
 559 u8 flash_read8(void *addr)
 560 {
 561         return __raw_readb(addr + 1);
 562 }
 563
 564 void flash_write16(u16 val, void *addr)
 565 {
 566         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 567
 568         __raw_writew(shftval, addr);
 569 }
 570
 571 u16 flash_read16(void *addr)
 572 {
 573         u16 val = __raw_readw(addr);
 574
 575         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 576 }
 577
 578 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 579 static void convert_flash_bank(char bank)
 580 {
 581         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 582
 583         printf("Now switch to boot from flash bank %d.\n", bank);
 584         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 585         cpld_data->vbank = bank;
 586
 587         printf("Reset board to enable configuration.\n");
 588         cpld_data->system_rst = CONFIG_RESET;
 589 }
 590
 591 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 592                           char * const argv[])
 593 {
 594         if (argc != 2)
 595                 return CMD_RET_USAGE;
 596         if (strcmp(argv[1], "0") == 0)
 597                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 598         else if (strcmp(argv[1], "1") == 0)
 599                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 600         else
 601                 return CMD_RET_USAGE;
 602
 603         return 0;
 604 }
 605
 606 U_BOOT_CMD(
 607         boot_bank, 2, 0, flash_bank_cmd,
 608         "Flash bank Selection Control",
 609         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 610 );
 611
 612 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 613                           char * const argv[])
 614 {
 615         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 616
 617         if (argc > 2)
 618                 return CMD_RET_USAGE;
 619         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 620                 cpld_data->system_rst = CONFIG_RESET;
 621         else if (strcmp(argv[1], "init") == 0)
 622                 cpld_data->global_rst = INIT_RESET;
 623         else
 624                 return CMD_RET_USAGE;
 625
 626         return 0;
 627 }
 628
 629 U_BOOT_CMD(
 630         cpld_reset, 2, 0, cpld_reset_cmd,
 631         "Reset via CPLD",
 632         "conf\n"
 633         "       -reset with current CPLD configuration\n"
 634         "init\n"
 635         "       -reset and initial CPLD configuration with default value"
 636
 637 );
 638
 639 static void convert_serdes_mux(int type, int need_reset)
 640 {
 641         char current_serdes;
 642         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 643
 644         current_serdes = cpld_data->serdes_mux;
 645
 646         switch (type) {
 647         case LANEB_SATA:
 648                 current_serdes &= ~MASK_LANE_B;
 649                 break;
 650         case LANEB_SGMII1:
 651                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 652                 break;
 653         case LANEC_SGMII1:
 654                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 655                 break;
 656         case LANED_SGMII2:
 657                 current_serdes |= MASK_LANE_D;
 658                 break;
 659         case LANEC_PCIEX1:
 660                 current_serdes |= MASK_LANE_C;
 661                 break;
 662         case (LANED_PCIEX2 | LANEC_PCIEX1):
 663                 current_serdes |= MASK_LANE_C;
 664                 current_serdes &= ~MASK_LANE_D;
 665                 break;
 666         default:
 667                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 668                 return;
 669         }
 670
 671         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 672         cpld_data->serdes_mux = current_serdes;
 673
 674         if (need_reset == 1) {
 675                 printf("Reset board to enable configuration\n");
 676                 cpld_data->system_rst = CONFIG_RESET;
 677         }
 678 }
 679
 680 void print_serdes_mux(void)
 681 {
 682         char current_serdes;
 683         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 684
 685         current_serdes = cpld_data->serdes_mux;
 686
 687         printf("Serdes Lane B: ");
 688         if ((current_serdes & MASK_LANE_B) == 0)
 689                 printf("SATA,\n");
 690         else
 691                 printf("SGMII 1,\n");
 692
 693         printf("Serdes Lane C: ");
 694         if ((current_serdes & MASK_LANE_C) == 0)
 695                 printf("SGMII 1,\n");
 696         else
 697                 printf("PCIe,\n");
 698
 699         printf("Serdes Lane D: ");
 700         if ((current_serdes & MASK_LANE_D) == 0)
 701                 printf("PCIe,\n");
 702         else
 703                 printf("SGMII 2,\n");
 704
 705         printf("SGMII 1 is on lane ");
 706         if ((current_serdes & MASK_SGMII) == 0)
 707                 printf("C.\n");
 708         else
 709                 printf("B.\n");
 710 }
 711
 712 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 713                           char * const argv[])
 714 {
 715         if (argc != 2)
 716                 return CMD_RET_USAGE;
 717         if (strcmp(argv[1], "sata") == 0) {
 718                 printf("Set serdes lane B to SATA.\n");
 719                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 720         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 721                 printf("Set serdes lane B to SGMII 1.\n");
 722                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 723         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 724                 printf("Set serdes lane C to SGMII 1.\n");
 725                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 726         } else if (strcmp(argv[1], "sgmii2") == 0) {
 727                 printf("Set serdes lane D to SGMII 2.\n");
 728                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 729         } else if (strcmp(argv[1], "pciex1") == 0) {
 730                 printf("Set serdes lane C to PCIe X1.\n");
 731                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 732         } else if (strcmp(argv[1], "pciex2") == 0) {
 733                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 734                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 735         } else if (strcmp(argv[1], "show") == 0) {
 736                 print_serdes_mux();
 737         } else {
 738                 return CMD_RET_USAGE;
 739         }
 740
 741         return 0;
 742 }
 743
 744 U_BOOT_CMD(
 745         lane_bank, 2, 0, serdes_mux_cmd,
 746         "Multiplexed function setting for SerDes Lanes",
 747         "sata\n"
 748         "       -change lane B to sata\n"
 749         "lane_bank sgmii1b\n"
 750         "       -change lane B to SGMII1\n"
 751         "lane_bank sgmii1c\n"
 752         "       -change lane C to SGMII1\n"
 753         "lane_bank sgmii2\n"
 754         "       -change lane D to SGMII2\n"
 755         "lane_bank pciex1\n"
 756         "       -change lane C to PCIeX1\n"
 757         "lane_bank pciex2\n"
 758         "       -change lane C & lane D to PCIeX2\n"
 759         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 760 );
 761 #endif