board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <i2c.h>
   9 #include <init.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_devdis.h>
  15 #include <asm/arch/ls102xa_soc.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_csu.h>
  19 #include <fsl_ifc.h>
  20 #include <fsl_immap.h>
  21 #include <netdev.h>
  22 #include <fsl_mdio.h>
  23 #include <tsec.h>
  24 #include <fsl_sec.h>
  25 #include <fsl_devdis.h>
  26 #include <spl.h>
  27 #include "../common/sleep.h"
  28 #ifdef CONFIG_U_QE
  29 #include <fsl_qe.h>
  30 #endif
  31 #include <fsl_validate.h>
  32
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define VERSION_MASK            0x00FF
  37 #define BANK_MASK               0x0001
  38 #define CONFIG_RESET            0x1
  39 #define INIT_RESET              0x1
  40
  41 #define CPLD_SET_MUX_SERDES     0x20
  42 #define CPLD_SET_BOOT_BANK      0x40
  43
  44 #define BOOT_FROM_UPPER_BANK    0x0
  45 #define BOOT_FROM_LOWER_BANK    0x1
  46
  47 #define LANEB_SATA              (0x01)
  48 #define LANEB_SGMII1            (0x02)
  49 #define LANEC_SGMII1            (0x04)
  50 #define LANEC_PCIEX1            (0x08)
  51 #define LANED_PCIEX2            (0x10)
  52 #define LANED_SGMII2            (0x20)
  53
  54 #define MASK_LANE_B             0x1
  55 #define MASK_LANE_C             0x2
  56 #define MASK_LANE_D             0x4
  57 #define MASK_SGMII              0x8
  58
  59 #define KEEP_STATUS             0x0
  60 #define NEED_RESET              0x1
  61
  62 #define SOFT_MUX_ON_I2C3_IFC    0x2
  63 #define SOFT_MUX_ON_CAN3_USB2   0x8
  64 #define SOFT_MUX_ON_QE_LCD      0x10
  65
  66 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  67 #define PIN_I2C3_IFC_MUX_IFC    0x1
  68 #define PIN_CAN3_USB2_MUX_USB2  0x0
  69 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  70 #define PIN_QE_LCD_MUX_LCD      0x0
  71 #define PIN_QE_LCD_MUX_QE       0x1
  72
  73 struct cpld_data {
  74         u8 cpld_ver;            /* cpld revision */
  75         u8 cpld_ver_sub;        /* cpld sub revision */
  76         u8 pcba_ver;            /* pcb revision number */
  77         u8 system_rst;          /* reset system by cpld */
  78         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  79         u8 cfg_rcw_src1;        /* Reset config word 1 */
  80         u8 cfg_rcw_src2;        /* Reset config word 2 */
  81         u8 vbank;               /* Flash bank selection Control */
  82         u8 gpio;                /* GPIO for TWR-ELEV */
  83         u8 i2c3_ifc_mux;
  84         u8 mux_spi2;
  85         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  86         u8 qe_lcd_mux;          /* QE and LCD Selection */
  87         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  88         u8 global_rst;          /* reset with init CPLD reg to default */
  89         u8 rev1;                /* Reserved */
  90         u8 rev2;                /* Reserved */
  91 };
  92
  93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  94 static void cpld_show(void)
  95 {
  96         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  97
  98         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
  99                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 100                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 101                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 102                in_8(&cpld_data->vbank) & BANK_MASK);
 103
 104 #ifdef CONFIG_DEBUG
 105         printf("soft_mux_on =%x\n",
 106                in_8(&cpld_data->soft_mux_on));
 107         printf("cfg_rcw_src1 =%x\n",
 108                in_8(&cpld_data->cfg_rcw_src1));
 109         printf("cfg_rcw_src2 =%x\n",
 110                in_8(&cpld_data->cfg_rcw_src2));
 111         printf("vbank =%x\n",
 112                in_8(&cpld_data->vbank));
 113         printf("gpio =%x\n",
 114                in_8(&cpld_data->gpio));
 115         printf("i2c3_ifc_mux =%x\n",
 116                in_8(&cpld_data->i2c3_ifc_mux));
 117         printf("mux_spi2 =%x\n",
 118                in_8(&cpld_data->mux_spi2));
 119         printf("can3_usb2_mux =%x\n",
 120                in_8(&cpld_data->can3_usb2_mux));
 121         printf("qe_lcd_mux =%x\n",
 122                in_8(&cpld_data->qe_lcd_mux));
 123         printf("serdes_mux =%x\n",
 124                in_8(&cpld_data->serdes_mux));
 125 #endif
 126 }
 127 #endif
 128
 129 int checkboard(void)
 130 {
 131         puts("Board: LS1021ATWR\n");
 132 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 133         cpld_show();
 134 #endif
 135
 136         return 0;
 137 }
 138
 139 void ddrmc_init(void)
 140 {
 141         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 142         u32 temp_sdram_cfg, tmp;
 143
 144         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 145
 146         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 147         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 148
 149         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 150         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 151         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 152         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 153         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 154         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 155
 156 #ifdef CONFIG_DEEP_SLEEP
 157         if (is_warm_boot()) {
 158                 out_be32(&ddr->sdram_cfg_2,
 159                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 160                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 161                 out_be32(&ddr->init_ext_addr, (1 << 31));
 162
 163                 /* DRAM VRef will not be trained */
 164                 out_be32(&ddr->ddr_cdr2,
 165                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 166         } else
 167 #endif
 168         {
 169                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 170                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 171         }
 172
 173         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 174         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 175
 176         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 177
 178         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 179
 180         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 181         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 182
 183         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 184
 185         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 186         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 187
 188         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 189
 190         /* DDR erratum A-009942 */
 191         tmp = in_be32(&ddr->debug[28]);
 192         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 193
 194         udelay(1);
 195
 196 #ifdef CONFIG_DEEP_SLEEP
 197         if (is_warm_boot()) {
 198                 /* enter self-refresh */
 199                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 200                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 201                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 202
 203                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 204         } else
 205 #endif
 206                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 207
 208         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 209
 210 #ifdef CONFIG_DEEP_SLEEP
 211         if (is_warm_boot()) {
 212                 /* exit self-refresh */
 213                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 214                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 215                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 216         }
 217 #endif
 218 }
 219
 220 int dram_init(void)
 221 {
 222 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 223         ddrmc_init();
 224 #endif
 225
 226         erratum_a008850_post();
 227
 228         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 229
 230 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 231         fsl_dp_resume();
 232 #endif
 233
 234         return 0;
 235 }
 236
 237 int board_eth_init(bd_t *bis)
 238 {
 239         return pci_eth_init(bis);
 240 }
 241
 242 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 243 static void convert_serdes_mux(int type, int need_reset)
 244 {
 245         char current_serdes;
 246         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 247
 248         current_serdes = cpld_data->serdes_mux;
 249
 250         switch (type) {
 251         case LANEB_SATA:
 252                 current_serdes &= ~MASK_LANE_B;
 253                 break;
 254         case LANEB_SGMII1:
 255                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 256                 break;
 257         case LANEC_SGMII1:
 258                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 259                 break;
 260         case LANED_SGMII2:
 261                 current_serdes |= MASK_LANE_D;
 262                 break;
 263         case LANEC_PCIEX1:
 264                 current_serdes |= MASK_LANE_C;
 265                 break;
 266         case (LANED_PCIEX2 | LANEC_PCIEX1):
 267                 current_serdes |= MASK_LANE_C;
 268                 current_serdes &= ~MASK_LANE_D;
 269                 break;
 270         default:
 271                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 272                 return;
 273         }
 274
 275         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 276         cpld_data->serdes_mux = current_serdes;
 277
 278         if (need_reset == 1) {
 279                 printf("Reset board to enable configuration\n");
 280                 cpld_data->system_rst = CONFIG_RESET;
 281         }
 282 }
 283
 284 int config_serdes_mux(void)
 285 {
 286         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 287         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 288
 289         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 290         switch (protocol) {
 291         case 0x10:
 292                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 293                 convert_serdes_mux(LANED_PCIEX2 |
 294                                 LANEC_PCIEX1, KEEP_STATUS);
 295                 break;
 296         case 0x20:
 297                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 298                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 299                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 300                 break;
 301         case 0x30:
 302                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 303                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 304                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 305                 break;
 306         case 0x70:
 307                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 308                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 309                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 310                 break;
 311         }
 312
 313         return 0;
 314 }
 315 #endif
 316
 317 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 318 int config_board_mux(void)
 319 {
 320         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 321         int conflict_flag;
 322
 323         conflict_flag = 0;
 324         if (hwconfig("i2c3")) {
 325                 conflict_flag++;
 326                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 327                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 328         }
 329
 330         if (hwconfig("ifc")) {
 331                 conflict_flag++;
 332                 /* some signals can not enable simultaneous*/
 333                 if (conflict_flag > 1)
 334                         goto conflict;
 335                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 336                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 337         }
 338
 339         conflict_flag = 0;
 340         if (hwconfig("usb2")) {
 341                 conflict_flag++;
 342                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 343                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 344         }
 345
 346         if (hwconfig("can3")) {
 347                 conflict_flag++;
 348                 /* some signals can not enable simultaneous*/
 349                 if (conflict_flag > 1)
 350                         goto conflict;
 351                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 352                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 353         }
 354
 355         conflict_flag = 0;
 356         if (hwconfig("lcd")) {
 357                 conflict_flag++;
 358                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 359                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 360         }
 361
 362         if (hwconfig("qe")) {
 363                 conflict_flag++;
 364                 /* some signals can not enable simultaneous*/
 365                 if (conflict_flag > 1)
 366                         goto conflict;
 367                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 368                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 369         }
 370
 371         return 0;
 372
 373 conflict:
 374         printf("WARNING: pin conflict! MUX setting may failed!\n");
 375         return 0;
 376 }
 377 #endif
 378
 379 int board_early_init_f(void)
 380 {
 381         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 382
 383 #ifdef CONFIG_TSEC_ENET
 384         /* clear BD & FR bits for BE BD's and frame data */
 385         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 386         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 387 #endif
 388
 389 #ifdef CONFIG_FSL_IFC
 390         init_early_memctl_regs();
 391 #endif
 392
 393         arch_soc_init();
 394
 395 #if defined(CONFIG_DEEP_SLEEP)
 396         if (is_warm_boot()) {
 397                 timer_init();
 398                 dram_init();
 399         }
 400 #endif
 401
 402         return 0;
 403 }
 404
 405 #ifdef CONFIG_SPL_BUILD
 406 void board_init_f(ulong dummy)
 407 {
 408         void (*second_uboot)(void);
 409
 410         /* Clear the BSS */
 411         memset(__bss_start, 0, __bss_end - __bss_start);
 412
 413         get_clocks();
 414
 415 #if defined(CONFIG_DEEP_SLEEP)
 416         if (is_warm_boot())
 417                 fsl_dp_disable_console();
 418 #endif
 419
 420         preloader_console_init();
 421
 422         timer_init();
 423         dram_init();
 424
 425         /* Allow OCRAM access permission as R/W */
 426 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 427         enable_layerscape_ns_access();
 428 #endif
 429
 430         /*
 431          * if it is woken up from deep sleep, then jump to second
 432          * stage uboot and continue executing without recopying
 433          * it from SD since it has already been reserved in memeory
 434          * in last boot.
 435          */
 436         if (is_warm_boot()) {
 437                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 438                 second_uboot();
 439         }
 440
 441         board_init_r(NULL, 0);
 442 }
 443 #endif
 444
 445 #ifdef CONFIG_DEEP_SLEEP
 446 /* program the regulator (MC34VR500) to support deep sleep */
 447 void ls1twr_program_regulator(void)
 448 {
 449         unsigned int i2c_bus;
 450         u8 i2c_device_id;
 451
 452 #define LS1TWR_I2C_BUS_MC34VR500        1
 453 #define MC34VR500_ADDR                  0x8
 454 #define MC34VR500_DEVICEID              0x4
 455 #define MC34VR500_DEVICEID_MASK         0x0f
 456
 457         i2c_bus = i2c_get_bus_num();
 458         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 459         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 460                                         MC34VR500_DEVICEID_MASK;
 461         if (i2c_device_id != MC34VR500_DEVICEID) {
 462                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 463                 return;
 464         }
 465
 466         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 467         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 468         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 469         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 470         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 471
 472         i2c_set_bus_num(i2c_bus);
 473 }
 474 #endif
 475
 476 int board_init(void)
 477 {
 478 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 479         erratum_a010315();
 480 #endif
 481
 482 #ifndef CONFIG_SYS_FSL_NO_SERDES
 483         fsl_serdes_init();
 484 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 485         config_serdes_mux();
 486 #endif
 487 #endif
 488
 489         ls102xa_smmu_stream_id_init();
 490
 491 #ifdef CONFIG_U_QE
 492         u_qe_init();
 493 #endif
 494
 495 #ifdef CONFIG_DEEP_SLEEP
 496         ls1twr_program_regulator();
 497 #endif
 498         return 0;
 499 }
 500
 501 #if defined(CONFIG_SPL_BUILD)
 502 void spl_board_init(void)
 503 {
 504         ls102xa_smmu_stream_id_init();
 505 }
 506 #endif
 507
 508 #ifdef CONFIG_BOARD_LATE_INIT
 509 int board_late_init(void)
 510 {
 511 #ifdef CONFIG_CHAIN_OF_TRUST
 512         fsl_setenv_chain_of_trust();
 513 #endif
 514
 515         return 0;
 516 }
 517 #endif
 518
 519 #if defined(CONFIG_MISC_INIT_R)
 520 int misc_init_r(void)
 521 {
 522 #ifdef CONFIG_FSL_DEVICE_DISABLE
 523         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 524 #endif
 525 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 526         config_board_mux();
 527 #endif
 528
 529 #ifdef CONFIG_FSL_CAAM
 530         return sec_init();
 531 #endif
 532 }
 533 #endif
 534
 535 #if defined(CONFIG_DEEP_SLEEP)
 536 void board_sleep_prepare(void)
 537 {
 538 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 539         enable_layerscape_ns_access();
 540 #endif
 541 }
 542 #endif
 543
 544 int ft_board_setup(void *blob, bd_t *bd)
 545 {
 546         ft_cpu_setup(blob, bd);
 547
 548 #ifdef CONFIG_PCI
 549         ft_pci_setup(blob, bd);
 550 #endif
 551
 552         return 0;
 553 }
 554
 555 u8 flash_read8(void *addr)
 556 {
 557         return __raw_readb(addr + 1);
 558 }
 559
 560 void flash_write16(u16 val, void *addr)
 561 {
 562         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 563
 564         __raw_writew(shftval, addr);
 565 }
 566
 567 u16 flash_read16(void *addr)
 568 {
 569         u16 val = __raw_readw(addr);
 570
 571         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 572 }
 573
 574 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 575         && !defined(CONFIG_SPL_BUILD)
 576 static void convert_flash_bank(char bank)
 577 {
 578         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 579
 580         printf("Now switch to boot from flash bank %d.\n", bank);
 581         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 582         cpld_data->vbank = bank;
 583
 584         printf("Reset board to enable configuration.\n");
 585         cpld_data->system_rst = CONFIG_RESET;
 586 }
 587
 588 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 589                           char * const argv[])
 590 {
 591         if (argc != 2)
 592                 return CMD_RET_USAGE;
 593         if (strcmp(argv[1], "0") == 0)
 594                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 595         else if (strcmp(argv[1], "1") == 0)
 596                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 597         else
 598                 return CMD_RET_USAGE;
 599
 600         return 0;
 601 }
 602
 603 U_BOOT_CMD(
 604         boot_bank, 2, 0, flash_bank_cmd,
 605         "Flash bank Selection Control",
 606         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 607 );
 608
 609 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 610                           char * const argv[])
 611 {
 612         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 613
 614         if (argc > 2)
 615                 return CMD_RET_USAGE;
 616         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 617                 cpld_data->system_rst = CONFIG_RESET;
 618         else if (strcmp(argv[1], "init") == 0)
 619                 cpld_data->global_rst = INIT_RESET;
 620         else
 621                 return CMD_RET_USAGE;
 622
 623         return 0;
 624 }
 625
 626 U_BOOT_CMD(
 627         cpld_reset, 2, 0, cpld_reset_cmd,
 628         "Reset via CPLD",
 629         "conf\n"
 630         "       -reset with current CPLD configuration\n"
 631         "init\n"
 632         "       -reset and initial CPLD configuration with default value"
 633
 634 );
 635
 636 static void print_serdes_mux(void)
 637 {
 638         char current_serdes;
 639         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 640
 641         current_serdes = cpld_data->serdes_mux;
 642
 643         printf("Serdes Lane B: ");
 644         if ((current_serdes & MASK_LANE_B) == 0)
 645                 printf("SATA,\n");
 646         else
 647                 printf("SGMII 1,\n");
 648
 649         printf("Serdes Lane C: ");
 650         if ((current_serdes & MASK_LANE_C) == 0)
 651                 printf("SGMII 1,\n");
 652         else
 653                 printf("PCIe,\n");
 654
 655         printf("Serdes Lane D: ");
 656         if ((current_serdes & MASK_LANE_D) == 0)
 657                 printf("PCIe,\n");
 658         else
 659                 printf("SGMII 2,\n");
 660
 661         printf("SGMII 1 is on lane ");
 662         if ((current_serdes & MASK_SGMII) == 0)
 663                 printf("C.\n");
 664         else
 665                 printf("B.\n");
 666 }
 667
 668 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 669                           char * const argv[])
 670 {
 671         if (argc != 2)
 672                 return CMD_RET_USAGE;
 673         if (strcmp(argv[1], "sata") == 0) {
 674                 printf("Set serdes lane B to SATA.\n");
 675                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 676         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 677                 printf("Set serdes lane B to SGMII 1.\n");
 678                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 679         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 680                 printf("Set serdes lane C to SGMII 1.\n");
 681                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 682         } else if (strcmp(argv[1], "sgmii2") == 0) {
 683                 printf("Set serdes lane D to SGMII 2.\n");
 684                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 685         } else if (strcmp(argv[1], "pciex1") == 0) {
 686                 printf("Set serdes lane C to PCIe X1.\n");
 687                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 688         } else if (strcmp(argv[1], "pciex2") == 0) {
 689                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 690                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 691         } else if (strcmp(argv[1], "show") == 0) {
 692                 print_serdes_mux();
 693         } else {
 694                 return CMD_RET_USAGE;
 695         }
 696
 697         return 0;
 698 }
 699
 700 U_BOOT_CMD(
 701         lane_bank, 2, 0, serdes_mux_cmd,
 702         "Multiplexed function setting for SerDes Lanes",
 703         "sata\n"
 704         "       -change lane B to sata\n"
 705         "lane_bank sgmii1b\n"
 706         "       -change lane B to SGMII1\n"
 707         "lane_bank sgmii1c\n"
 708         "       -change lane C to SGMII1\n"
 709         "lane_bank sgmii2\n"
 710         "       -change lane D to SGMII2\n"
 711         "lane_bank pciex1\n"
 712         "       -change lane C to PCIeX1\n"
 713         "lane_bank pciex2\n"
 714         "       -change lane C & lane D to PCIeX2\n"
 715         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 716 );
 717 #endif