board/freescale/ls1021atsn/ls1021atsn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2016-2019 NXP Semiconductors
   3  */
   4 #include <common.h>
   5 #include <asm/arch-ls102xa/ls102xa_soc.h>
   6 #include <asm/arch/ls102xa_devdis.h>
   7 #include <asm/arch/immap_ls102xa.h>
   8 #include <asm/arch/ls102xa_soc.h>
   9 #include <asm/arch/fsl_serdes.h>
  10 #include "../common/sleep.h"
  11 #include <fsl_validate.h>
  12 #include <fsl_immap.h>
  13 #include <fsl_csu.h>
  14 #include <netdev.h>
  15 #include <spl.h>
  16 #ifdef CONFIG_U_QE
  17 #include <fsl_qe.h>
  18 #endif
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static void ddrmc_init(void)
  23 {
  24 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  25         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  26         u32 temp_sdram_cfg, tmp;
  27
  28         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  29
  30         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  31         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  32
  33         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  34         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  35         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  36         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  37         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  38         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  39
  40 #ifdef CONFIG_DEEP_SLEEP
  41         if (is_warm_boot()) {
  42                 out_be32(&ddr->sdram_cfg_2,
  43                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  44                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  45                 out_be32(&ddr->init_ext_addr, (1 << 31));
  46
  47                 /* DRAM VRef will not be trained */
  48                 out_be32(&ddr->ddr_cdr2,
  49                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  50         } else
  51 #endif
  52         {
  53                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  54                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  55         }
  56
  57         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  58         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  59
  60         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  61
  62         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  63
  64         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  65         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  66
  67         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  68
  69         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  70         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  71
  72         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  73
  74         /* DDR erratum A-009942 */
  75         tmp = in_be32(&ddr->debug[28]);
  76         out_be32(&ddr->debug[28], tmp | 0x0070006f);
  77
  78         udelay(1);
  79
  80 #ifdef CONFIG_DEEP_SLEEP
  81         if (is_warm_boot()) {
  82                 /* enter self-refresh */
  83                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  84                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  85                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  86
  87                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  88         } else
  89 #endif
  90                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  91
  92         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  93
  94 #ifdef CONFIG_DEEP_SLEEP
  95         if (is_warm_boot()) {
  96                 /* exit self-refresh */
  97                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  98                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  99                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 100         }
 101 #endif
 102 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 103 }
 104
 105 int dram_init(void)
 106 {
 107         ddrmc_init();
 108
 109         erratum_a008850_post();
 110
 111         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 112
 113 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 114         fsl_dp_resume();
 115 #endif
 116
 117         return 0;
 118 }
 119
 120 int board_eth_init(bd_t *bis)
 121 {
 122         return pci_eth_init(bis);
 123 }
 124
 125 int board_early_init_f(void)
 126 {
 127         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 128
 129 #ifdef CONFIG_TSEC_ENET
 130         /*
 131          * Clear BD & FR bits for big endian BD's and frame data (aka set
 132          * correct eTSEC endianness). This is crucial in ensuring that it does
 133          * not report Data Parity Errors in its RX/TX FIFOs when attempting to
 134          * send traffic.
 135          */
 136         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 137         /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
 138         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 139 #endif
 140
 141         arch_soc_init();
 142
 143 #if defined(CONFIG_DEEP_SLEEP)
 144         if (is_warm_boot()) {
 145                 timer_init();
 146                 dram_init();
 147         }
 148 #endif
 149
 150         return 0;
 151 }
 152
 153 #ifdef CONFIG_SPL_BUILD
 154 void board_init_f(ulong dummy)
 155 {
 156         void (*second_uboot)(void);
 157
 158         /* Clear the BSS */
 159         memset(__bss_start, 0, __bss_end - __bss_start);
 160
 161         get_clocks();
 162
 163 #if defined(CONFIG_DEEP_SLEEP)
 164         if (is_warm_boot())
 165                 fsl_dp_disable_console();
 166 #endif
 167
 168         preloader_console_init();
 169
 170         dram_init();
 171
 172         /* Allow OCRAM access permission as R/W */
 173 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 174         enable_layerscape_ns_access();
 175         enable_layerscape_ns_access();
 176 #endif
 177
 178         /*
 179          * if it is woken up from deep sleep, then jump to second
 180          * stage U-Boot and continue executing without recopying
 181          * it from SD since it has already been reserved in memory
 182          * in last boot.
 183          */
 184         if (is_warm_boot()) {
 185                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 186                 second_uboot();
 187         }
 188
 189         board_init_r(NULL, 0);
 190 }
 191 #endif
 192
 193 int board_init(void)
 194 {
 195 #ifndef CONFIG_SYS_FSL_NO_SERDES
 196         fsl_serdes_init();
 197 #endif
 198         ls102xa_smmu_stream_id_init();
 199
 200 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 201         enable_layerscape_ns_access();
 202 #endif
 203
 204 #ifdef CONFIG_U_QE
 205         u_qe_init();
 206 #endif
 207
 208         return 0;
 209 }
 210
 211 #if defined(CONFIG_SPL_BUILD)
 212 void spl_board_init(void)
 213 {
 214         ls102xa_smmu_stream_id_init();
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_BOARD_LATE_INIT
 219 int board_late_init(void)
 220 {
 221 #ifdef CONFIG_CHAIN_OF_TRUST
 222         fsl_setenv_chain_of_trust();
 223 #endif
 224
 225         return 0;
 226 }
 227 #endif
 228
 229 #if defined(CONFIG_MISC_INIT_R)
 230 int misc_init_r(void)
 231 {
 232 #ifdef CONFIG_FSL_DEVICE_DISABLE
 233         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 234 #endif
 235
 236 #ifdef CONFIG_FSL_CAAM
 237         return sec_init();
 238 #endif
 239 }
 240 #endif
 241
 242 #if defined(CONFIG_DEEP_SLEEP)
 243 void board_sleep_prepare(void)
 244 {
 245 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 246         enable_layerscape_ns_access();
 247 #endif
 248 }
 249 #endif
 250
 251 int ft_board_setup(void *blob, bd_t *bd)
 252 {
 253         ft_cpu_setup(blob, bd);
 254
 255 #ifdef CONFIG_PCI
 256         ft_pci_setup(blob, bd);
 257 #endif
 258
 259         return 0;
 260 }