arm: juno: Use PSCI based reset
[oweals/u-boot.git] / board / freescale / ls1021atsn / ls1021atsn.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2019 NXP Semiconductors
3  */
4 #include <common.h>
5 #include <clock_legacy.h>
6 #include <fdt_support.h>
7 #include <init.h>
8 #include <asm/arch-ls102xa/ls102xa_soc.h>
9 #include <asm/arch/ls102xa_devdis.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ls102xa_soc.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include "../common/sleep.h"
14 #include <fsl_validate.h>
15 #include <fsl_immap.h>
16 #include <fsl_csu.h>
17 #include <netdev.h>
18 #include <spl.h>
19 #ifdef CONFIG_U_QE
20 #include <fsl_qe.h>
21 #endif
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 static void ddrmc_init(void)
26 {
27 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
28         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
29         u32 temp_sdram_cfg, tmp;
30
31         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
32
33         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
34         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
35
36         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
37         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
38         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
39         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
40         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
41         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
42
43 #ifdef CONFIG_DEEP_SLEEP
44         if (is_warm_boot()) {
45                 out_be32(&ddr->sdram_cfg_2,
46                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
47                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
48                 out_be32(&ddr->init_ext_addr, (1 << 31));
49
50                 /* DRAM VRef will not be trained */
51                 out_be32(&ddr->ddr_cdr2,
52                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
53         } else
54 #endif
55         {
56                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
57                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
58         }
59
60         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
61         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
62
63         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
64
65         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
66
67         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
68         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
69
70         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
71
72         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
73         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
74
75         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
76
77         /* DDR erratum A-009942 */
78         tmp = in_be32(&ddr->debug[28]);
79         out_be32(&ddr->debug[28], tmp | 0x0070006f);
80
81         udelay(1);
82
83 #ifdef CONFIG_DEEP_SLEEP
84         if (is_warm_boot()) {
85                 /* enter self-refresh */
86                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
87                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
88                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
89
90                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
91         } else
92 #endif
93                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
94
95         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
96
97 #ifdef CONFIG_DEEP_SLEEP
98         if (is_warm_boot()) {
99                 /* exit self-refresh */
100                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
101                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
102                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
103         }
104 #endif
105 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
106 }
107
108 int dram_init(void)
109 {
110         ddrmc_init();
111
112         erratum_a008850_post();
113
114         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
115
116 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
117         fsl_dp_resume();
118 #endif
119
120         return 0;
121 }
122
123 int board_eth_init(bd_t *bis)
124 {
125         return pci_eth_init(bis);
126 }
127
128 int board_early_init_f(void)
129 {
130         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
131
132 #ifdef CONFIG_TSEC_ENET
133         /*
134          * Clear BD & FR bits for big endian BD's and frame data (aka set
135          * correct eTSEC endianness). This is crucial in ensuring that it does
136          * not report Data Parity Errors in its RX/TX FIFOs when attempting to
137          * send traffic.
138          */
139         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
140         /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
141         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
142 #endif
143
144         arch_soc_init();
145
146 #if defined(CONFIG_DEEP_SLEEP)
147         if (is_warm_boot()) {
148                 timer_init();
149                 dram_init();
150         }
151 #endif
152
153         return 0;
154 }
155
156 #ifdef CONFIG_SPL_BUILD
157 void board_init_f(ulong dummy)
158 {
159         void (*second_uboot)(void);
160
161         /* Clear the BSS */
162         memset(__bss_start, 0, __bss_end - __bss_start);
163
164         get_clocks();
165
166 #if defined(CONFIG_DEEP_SLEEP)
167         if (is_warm_boot())
168                 fsl_dp_disable_console();
169 #endif
170
171         preloader_console_init();
172
173         dram_init();
174
175         /* Allow OCRAM access permission as R/W */
176 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
177         enable_layerscape_ns_access();
178         enable_layerscape_ns_access();
179 #endif
180
181         /*
182          * if it is woken up from deep sleep, then jump to second
183          * stage U-Boot and continue executing without recopying
184          * it from SD since it has already been reserved in memory
185          * in last boot.
186          */
187         if (is_warm_boot()) {
188                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
189                 second_uboot();
190         }
191
192         board_init_r(NULL, 0);
193 }
194 #endif
195
196 int board_init(void)
197 {
198 #ifndef CONFIG_SYS_FSL_NO_SERDES
199         fsl_serdes_init();
200 #endif
201         ls102xa_smmu_stream_id_init();
202
203 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
204         enable_layerscape_ns_access();
205 #endif
206
207 #ifdef CONFIG_U_QE
208         u_qe_init();
209 #endif
210
211         return 0;
212 }
213
214 #if defined(CONFIG_SPL_BUILD)
215 void spl_board_init(void)
216 {
217         ls102xa_smmu_stream_id_init();
218 }
219 #endif
220
221 #ifdef CONFIG_BOARD_LATE_INIT
222 int board_late_init(void)
223 {
224 #ifdef CONFIG_CHAIN_OF_TRUST
225         fsl_setenv_chain_of_trust();
226 #endif
227
228         return 0;
229 }
230 #endif
231
232 #if defined(CONFIG_MISC_INIT_R)
233 int misc_init_r(void)
234 {
235 #ifdef CONFIG_FSL_DEVICE_DISABLE
236         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
237 #endif
238
239 #ifdef CONFIG_FSL_CAAM
240         return sec_init();
241 #endif
242 }
243 #endif
244
245 #if defined(CONFIG_DEEP_SLEEP)
246 void board_sleep_prepare(void)
247 {
248 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
249         enable_layerscape_ns_access();
250 #endif
251 }
252 #endif
253
254 int ft_board_setup(void *blob, bd_t *bd)
255 {
256         ft_cpu_setup(blob, bd);
257
258 #ifdef CONFIG_PCI
259         ft_pci_setup(blob, bd);
260 #endif
261
262         return 0;
263 }