2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_soc.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
19 #include <fsl_esdhc.h>
23 #include <fsl_devdis.h>
24 #include <fsl_validate.h>
26 #include "../common/sleep.h"
27 #include "../common/qixis.h"
28 #include "ls1021aqds_qixis.h"
33 #define PIN_MUX_SEL_CAN 0x03
34 #define PIN_MUX_SEL_IIC2 0xa0
35 #define PIN_MUX_SEL_RGMII 0x00
36 #define PIN_MUX_SEL_SAI 0x0c
37 #define PIN_MUX_SEL_SDHC 0x00
39 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
40 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
48 MUX_TYPE_SD_PC_SA_SG_SG,
49 MUX_TYPE_SD_PC_SA_PC_SG,
61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
64 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
68 puts("Board: LS1021AQDS\n");
72 #elif CONFIG_QSPI_BOOT
75 sw = QIXIS_READ(brdcfg[0]);
76 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
79 printf("vBank: %d\n", sw);
87 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
90 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
91 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
92 QIXIS_READ(id), QIXIS_READ(arch));
94 printf("FPGA: v%d (%s), build %d\n",
95 (int)QIXIS_READ(scver), qixis_read_tag(buf),
96 (int)qixis_read_minor());
102 unsigned long get_board_sys_clk(void)
104 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
106 switch (sysclk_conf & 0x0f) {
107 case QIXIS_SYSCLK_64:
109 case QIXIS_SYSCLK_83:
111 case QIXIS_SYSCLK_100:
113 case QIXIS_SYSCLK_125:
115 case QIXIS_SYSCLK_133:
117 case QIXIS_SYSCLK_150:
119 case QIXIS_SYSCLK_160:
121 case QIXIS_SYSCLK_166:
127 unsigned long get_board_ddr_clk(void)
129 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
131 switch ((ddrclk_conf & 0x30) >> 4) {
132 case QIXIS_DDRCLK_100:
134 case QIXIS_DDRCLK_125:
136 case QIXIS_DDRCLK_133:
142 int select_i2c_ch_pca9547(u8 ch)
146 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
148 puts("PCA: failed to select proper channel\n");
158 * When resuming from deep sleep, the I2C channel may not be
159 * in the default channel. So, switch to the default channel
160 * before accessing DDR SPD.
162 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
163 return fsl_initdram();
166 #ifdef CONFIG_FSL_ESDHC
167 struct fsl_esdhc_cfg esdhc_cfg[1] = {
168 {CONFIG_SYS_FSL_ESDHC_ADDR},
171 int board_mmc_init(bd_t *bis)
173 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
175 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
179 int board_early_init_f(void)
181 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
183 #ifdef CONFIG_TSEC_ENET
184 /* clear BD & FR bits for BE BD's and frame data */
185 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
188 #ifdef CONFIG_FSL_IFC
189 init_early_memctl_regs();
194 #if defined(CONFIG_DEEP_SLEEP)
196 fsl_dp_disable_console();
202 #ifdef CONFIG_SPL_BUILD
203 void board_init_f(ulong dummy)
205 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
206 CONFIG_SYS_CCI400_OFFSET);
209 #ifdef CONFIG_NAND_BOOT
210 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
214 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
215 * NAND boot because IFC signals > IFC_AD7 are not enabled.
216 * This workaround changes RCW source to make all signals enabled.
218 porsr1 = in_be32(&gur->porsr1);
219 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
220 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
221 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
226 memset(__bss_start, 0, __bss_end - __bss_start);
228 #ifdef CONFIG_FSL_IFC
229 init_early_memctl_regs();
234 #if defined(CONFIG_DEEP_SLEEP)
236 fsl_dp_disable_console();
239 preloader_console_init();
241 #ifdef CONFIG_SPL_I2C_SUPPORT
245 major = get_soc_major_rev();
246 if (major == SOC_MAJOR_VER_1_0)
247 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
251 /* Allow OCRAM access permission as R/W */
252 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
253 enable_layerscape_ns_access();
256 board_init_r(NULL, 0);
260 void config_etseccm_source(int etsec_gtx_125_mux)
262 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
264 switch (etsec_gtx_125_mux) {
266 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
267 debug("etseccm set to GE0_CLK125\n");
271 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
272 debug("etseccm set to GE2_CLK125\n");
276 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
277 debug("etseccm set to GE1_CLK125\n");
281 printf("Error! trying to set etseccm to invalid value\n");
286 int config_board_mux(int ctrl_type)
290 reg12 = QIXIS_READ(brdcfg[12]);
291 reg14 = QIXIS_READ(brdcfg[14]);
295 config_etseccm_source(GE2_CLK125);
296 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
299 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
302 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
305 config_etseccm_source(GE2_CLK125);
306 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
309 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
311 case MUX_TYPE_SD_PCI4:
314 case MUX_TYPE_SD_PC_SA_SG_SG:
317 case MUX_TYPE_SD_PC_SA_PC_SG:
320 case MUX_TYPE_SD_PC_SG_SG:
324 printf("Wrong mux interface type\n");
328 QIXIS_WRITE(brdcfg[12], reg12);
329 QIXIS_WRITE(brdcfg[14], reg14);
334 int config_serdes_mux(void)
336 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
339 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
340 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
344 config_board_mux(MUX_TYPE_SD_PCI4);
347 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
350 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
353 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
356 printf("SRDS1 prtcl:0x%x\n", cfg);
363 #ifdef CONFIG_BOARD_LATE_INIT
364 int board_late_init(void)
366 #ifdef CONFIG_SCSI_AHCI_PLAT
369 #ifdef CONFIG_CHAIN_OF_TRUST
370 fsl_setenv_chain_of_trust();
377 int misc_init_r(void)
381 /* some signals can not enable simultaneous*/
383 if (hwconfig("sdhc"))
385 if (hwconfig("iic2"))
387 if (conflict_flag > 1) {
388 printf("WARNING: pin conflict !\n");
393 if (hwconfig("rgmii"))
399 if (conflict_flag > 1) {
400 printf("WARNING: pin conflict !\n");
405 config_board_mux(MUX_TYPE_CAN);
406 else if (hwconfig("rgmii"))
407 config_board_mux(MUX_TYPE_RGMII);
408 else if (hwconfig("sai"))
409 config_board_mux(MUX_TYPE_SAI);
411 if (hwconfig("iic2"))
412 config_board_mux(MUX_TYPE_IIC2);
413 else if (hwconfig("sdhc"))
414 config_board_mux(MUX_TYPE_SDHC);
416 #ifdef CONFIG_FSL_DEVICE_DISABLE
417 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
419 #ifdef CONFIG_FSL_CAAM
427 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
428 CONFIG_SYS_CCI400_OFFSET);
431 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
434 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
435 erratum_a009942_check_cpo();
437 major = get_soc_major_rev();
438 if (major == SOC_MAJOR_VER_1_0) {
439 /* Set CCI-400 control override register to
440 * enable barrier transaction */
441 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
444 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
446 #ifndef CONFIG_SYS_FSL_NO_SERDES
451 ls102xa_smmu_stream_id_init();
460 #if defined(CONFIG_DEEP_SLEEP)
461 void board_sleep_prepare(void)
463 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
464 CONFIG_SYS_CCI400_OFFSET);
467 major = get_soc_major_rev();
468 if (major == SOC_MAJOR_VER_1_0) {
469 /* Set CCI-400 control override register to
470 * enable barrier transaction */
471 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
475 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
476 enable_layerscape_ns_access();
481 int ft_board_setup(void *blob, bd_t *bd)
483 ft_cpu_setup(blob, bd);
486 ft_pci_setup(blob, bd);
492 u8 flash_read8(void *addr)
494 return __raw_readb(addr + 1);
497 void flash_write16(u16 val, void *addr)
499 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
501 __raw_writew(shftval, addr);
504 u16 flash_read16(void *addr)
506 u16 val = __raw_readw(addr);
508 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);