2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/pcie_layerscape.h>
15 #include <fsl_esdhc.h>
20 #include "../common/qixis.h"
21 #include "ls1021aqds_qixis.h"
23 #include "../../../drivers/qe/qe.h"
26 DECLARE_GLOBAL_DATA_PTR;
30 MUX_TYPE_SD_PC_SA_SG_SG,
31 MUX_TYPE_SD_PC_SA_PC_SG,
37 #ifndef CONFIG_QSPI_BOOT
40 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
44 puts("Board: LS1021AQDS\n");
48 #elif CONFIG_QSPI_BOOT
51 sw = QIXIS_READ(brdcfg[0]);
52 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
55 printf("vBank: %d\n", sw);
63 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
66 #ifndef CONFIG_QSPI_BOOT
67 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
68 QIXIS_READ(id), QIXIS_READ(arch));
70 printf("FPGA: v%d (%s), build %d\n",
71 (int)QIXIS_READ(scver), qixis_read_tag(buf),
72 (int)qixis_read_minor());
78 unsigned long get_board_sys_clk(void)
80 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
82 switch (sysclk_conf & 0x0f) {
87 case QIXIS_SYSCLK_100:
89 case QIXIS_SYSCLK_125:
91 case QIXIS_SYSCLK_133:
93 case QIXIS_SYSCLK_150:
95 case QIXIS_SYSCLK_160:
97 case QIXIS_SYSCLK_166:
103 unsigned long get_board_ddr_clk(void)
105 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
107 switch ((ddrclk_conf & 0x30) >> 4) {
108 case QIXIS_DDRCLK_100:
110 case QIXIS_DDRCLK_125:
112 case QIXIS_DDRCLK_133:
118 int select_i2c_ch_pca9547(u8 ch)
122 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
124 puts("PCA: failed to select proper channel\n");
134 * When resuming from deep sleep, the I2C channel may not be
135 * in the default channel. So, switch to the default channel
136 * before accessing DDR SPD.
138 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
139 gd->ram_size = initdram(0);
144 #ifdef CONFIG_FSL_ESDHC
145 struct fsl_esdhc_cfg esdhc_cfg[1] = {
146 {CONFIG_SYS_FSL_ESDHC_ADDR},
149 int board_mmc_init(bd_t *bis)
151 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
153 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
157 int board_early_init_f(void)
159 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
160 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
162 #ifdef CONFIG_TSEC_ENET
163 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
164 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
167 #ifdef CONFIG_FSL_IFC
168 init_early_memctl_regs();
171 #ifdef CONFIG_FSL_QSPI
172 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
175 /* Workaround for the issue that DDR could not respond to
176 * barrier transaction which is generated by executing DSB/ISB
177 * instruction. Set CCI-400 control override register to
178 * terminate the barrier transaction. After DDR is initialized,
179 * allow barrier transaction to DDR again */
180 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
185 #ifdef CONFIG_SPL_BUILD
186 void board_init_f(ulong dummy)
188 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
190 #ifdef CONFIG_NAND_BOOT
191 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
195 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
196 * NAND boot because IFC signals > IFC_AD7 are not enabled.
197 * This workaround changes RCW source to make all signals enabled.
199 porsr1 = in_be32(&gur->porsr1);
200 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
201 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
202 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
206 /* Set global data pointer */
210 memset(__bss_start, 0, __bss_end - __bss_start);
212 #ifdef CONFIG_FSL_IFC
213 init_early_memctl_regs();
218 preloader_console_init();
220 #ifdef CONFIG_SPL_I2C_SUPPORT
223 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
227 board_init_r(NULL, 0);
231 int config_board_mux(int ctrl_type)
235 reg12 = QIXIS_READ(brdcfg[12]);
238 case MUX_TYPE_SD_PCI4:
241 case MUX_TYPE_SD_PC_SA_SG_SG:
244 case MUX_TYPE_SD_PC_SA_PC_SG:
247 case MUX_TYPE_SD_PC_SG_SG:
251 printf("Wrong mux interface type\n");
255 QIXIS_WRITE(brdcfg[12], reg12);
260 int config_serdes_mux(void)
262 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
265 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
266 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
270 config_board_mux(MUX_TYPE_SD_PCI4);
273 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
276 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
279 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
282 printf("SRDS1 prtcl:0x%x\n", cfg);
289 #if defined(CONFIG_MISC_INIT_R)
290 int misc_init_r(void)
292 #ifdef CONFIG_FSL_CAAM
300 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
302 /* Set CCI-400 control override register to
303 * enable barrier transaction */
304 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
306 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
307 * All transactions are treated as non-shareable
309 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
310 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
311 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
313 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
315 #ifndef CONFIG_SYS_FSL_NO_SERDES
327 int ft_board_setup(void *blob, bd_t *bd)
329 ft_cpu_setup(blob, bd);
331 #ifdef CONFIG_PCIE_LAYERSCAPE
332 ft_pcie_setup(blob, bd);
338 u8 flash_read8(void *addr)
340 return __raw_readb(addr + 1);
343 void flash_write16(u16 val, void *addr)
345 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
347 __raw_writew(shftval, addr);
350 u16 flash_read16(void *addr)
352 u16 val = __raw_readw(addr);
354 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);