1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/ls102xa_devdis.h>
17 #include <fsl_esdhc.h>
21 #include <fsl_devdis.h>
22 #include <fsl_validate.h>
24 #include "../common/sleep.h"
25 #include "../common/qixis.h"
26 #include "ls1021aqds_qixis.h"
31 #define PIN_MUX_SEL_CAN 0x03
32 #define PIN_MUX_SEL_IIC2 0xa0
33 #define PIN_MUX_SEL_RGMII 0x00
34 #define PIN_MUX_SEL_SAI 0x0c
35 #define PIN_MUX_SEL_SDHC 0x00
37 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
38 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
46 MUX_TYPE_SD_PC_SA_SG_SG,
47 MUX_TYPE_SD_PC_SA_PC_SG,
59 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
66 puts("Board: LS1021AQDS\n");
70 #elif CONFIG_QSPI_BOOT
73 sw = QIXIS_READ(brdcfg[0]);
74 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
77 printf("vBank: %d\n", sw);
85 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
88 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
89 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
90 QIXIS_READ(id), QIXIS_READ(arch));
92 printf("FPGA: v%d (%s), build %d\n",
93 (int)QIXIS_READ(scver), qixis_read_tag(buf),
94 (int)qixis_read_minor());
100 unsigned long get_board_sys_clk(void)
102 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
104 switch (sysclk_conf & 0x0f) {
105 case QIXIS_SYSCLK_64:
107 case QIXIS_SYSCLK_83:
109 case QIXIS_SYSCLK_100:
111 case QIXIS_SYSCLK_125:
113 case QIXIS_SYSCLK_133:
115 case QIXIS_SYSCLK_150:
117 case QIXIS_SYSCLK_160:
119 case QIXIS_SYSCLK_166:
125 unsigned long get_board_ddr_clk(void)
127 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
129 switch ((ddrclk_conf & 0x30) >> 4) {
130 case QIXIS_DDRCLK_100:
132 case QIXIS_DDRCLK_125:
134 case QIXIS_DDRCLK_133:
140 int select_i2c_ch_pca9547(u8 ch)
144 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
146 puts("PCA: failed to select proper channel\n");
156 * When resuming from deep sleep, the I2C channel may not be
157 * in the default channel. So, switch to the default channel
158 * before accessing DDR SPD.
160 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 return fsl_initdram();
164 #ifdef CONFIG_FSL_ESDHC
165 struct fsl_esdhc_cfg esdhc_cfg[1] = {
166 {CONFIG_SYS_FSL_ESDHC_ADDR},
169 int board_mmc_init(bd_t *bis)
171 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
173 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
177 int board_early_init_f(void)
179 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
181 #ifdef CONFIG_TSEC_ENET
182 /* clear BD & FR bits for BE BD's and frame data */
183 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
186 #ifdef CONFIG_FSL_IFC
187 init_early_memctl_regs();
192 #if defined(CONFIG_DEEP_SLEEP)
194 fsl_dp_disable_console();
200 #ifdef CONFIG_SPL_BUILD
201 void board_init_f(ulong dummy)
203 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
204 CONFIG_SYS_CCI400_OFFSET);
207 #ifdef CONFIG_NAND_BOOT
208 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
212 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
213 * NAND boot because IFC signals > IFC_AD7 are not enabled.
214 * This workaround changes RCW source to make all signals enabled.
216 porsr1 = in_be32(&gur->porsr1);
217 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
218 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
219 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
224 memset(__bss_start, 0, __bss_end - __bss_start);
226 #ifdef CONFIG_FSL_IFC
227 init_early_memctl_regs();
232 #if defined(CONFIG_DEEP_SLEEP)
234 fsl_dp_disable_console();
237 preloader_console_init();
239 #ifdef CONFIG_SPL_I2C_SUPPORT
243 major = get_soc_major_rev();
244 if (major == SOC_MAJOR_VER_1_0)
245 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
250 /* Allow OCRAM access permission as R/W */
251 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
252 enable_layerscape_ns_access();
255 board_init_r(NULL, 0);
259 void config_etseccm_source(int etsec_gtx_125_mux)
261 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
263 switch (etsec_gtx_125_mux) {
265 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
266 debug("etseccm set to GE0_CLK125\n");
270 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
271 debug("etseccm set to GE2_CLK125\n");
275 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
276 debug("etseccm set to GE1_CLK125\n");
280 printf("Error! trying to set etseccm to invalid value\n");
285 int config_board_mux(int ctrl_type)
289 reg12 = QIXIS_READ(brdcfg[12]);
290 reg14 = QIXIS_READ(brdcfg[14]);
294 config_etseccm_source(GE2_CLK125);
295 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
298 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
301 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
304 config_etseccm_source(GE2_CLK125);
305 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
308 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
310 case MUX_TYPE_SD_PCI4:
313 case MUX_TYPE_SD_PC_SA_SG_SG:
316 case MUX_TYPE_SD_PC_SA_PC_SG:
319 case MUX_TYPE_SD_PC_SG_SG:
323 printf("Wrong mux interface type\n");
327 QIXIS_WRITE(brdcfg[12], reg12);
328 QIXIS_WRITE(brdcfg[14], reg14);
333 int config_serdes_mux(void)
335 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
338 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
339 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
343 config_board_mux(MUX_TYPE_SD_PCI4);
346 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
349 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
352 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
355 printf("SRDS1 prtcl:0x%x\n", cfg);
362 #ifdef CONFIG_BOARD_LATE_INIT
363 int board_late_init(void)
365 #ifdef CONFIG_CHAIN_OF_TRUST
366 fsl_setenv_chain_of_trust();
373 int misc_init_r(void)
377 /* some signals can not enable simultaneous*/
379 if (hwconfig("sdhc"))
381 if (hwconfig("iic2"))
383 if (conflict_flag > 1) {
384 printf("WARNING: pin conflict !\n");
389 if (hwconfig("rgmii"))
395 if (conflict_flag > 1) {
396 printf("WARNING: pin conflict !\n");
401 config_board_mux(MUX_TYPE_CAN);
402 else if (hwconfig("rgmii"))
403 config_board_mux(MUX_TYPE_RGMII);
404 else if (hwconfig("sai"))
405 config_board_mux(MUX_TYPE_SAI);
407 if (hwconfig("iic2"))
408 config_board_mux(MUX_TYPE_IIC2);
409 else if (hwconfig("sdhc"))
410 config_board_mux(MUX_TYPE_SDHC);
412 #ifdef CONFIG_FSL_DEVICE_DISABLE
413 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
415 #ifdef CONFIG_FSL_CAAM
423 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
424 CONFIG_SYS_CCI400_OFFSET);
427 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
430 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
431 erratum_a009942_check_cpo();
433 major = get_soc_major_rev();
434 if (major == SOC_MAJOR_VER_1_0) {
435 /* Set CCI-400 control override register to
436 * enable barrier transaction */
437 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
440 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
442 #ifndef CONFIG_SYS_FSL_NO_SERDES
447 ls102xa_smmu_stream_id_init();
456 #if defined(CONFIG_DEEP_SLEEP)
457 void board_sleep_prepare(void)
459 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
460 CONFIG_SYS_CCI400_OFFSET);
463 major = get_soc_major_rev();
464 if (major == SOC_MAJOR_VER_1_0) {
465 /* Set CCI-400 control override register to
466 * enable barrier transaction */
467 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
471 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
472 enable_layerscape_ns_access();
477 int ft_board_setup(void *blob, bd_t *bd)
479 ft_cpu_setup(blob, bd);
482 ft_pci_setup(blob, bd);
488 u8 flash_read8(void *addr)
490 return __raw_readb(addr + 1);
493 void flash_write16(u16 val, void *addr)
495 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
497 __raw_writew(shftval, addr);
500 u16 flash_read16(void *addr)
502 u16 val = __raw_readw(addr);
504 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);