board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <fsl_sec.h>
  20 #include <spl.h>
  21
  22 #include "../common/sleep.h"
  23 #include "../common/qixis.h"
  24 #include "ls1021aqds_qixis.h"
  25 #ifdef CONFIG_U_QE
  26 #include "../../../drivers/qe/qe.h"
  27 #endif
  28
  29 #define PIN_MUX_SEL_CAN         0x03
  30 #define PIN_MUX_SEL_IIC2        0xa0
  31 #define PIN_MUX_SEL_RGMII       0x00
  32 #define PIN_MUX_SEL_SAI         0x0c
  33 #define PIN_MUX_SEL_SDHC        0x00
  34
  35 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  36 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         MUX_TYPE_CAN,
  41         MUX_TYPE_IIC2,
  42         MUX_TYPE_RGMII,
  43         MUX_TYPE_SAI,
  44         MUX_TYPE_SDHC,
  45         MUX_TYPE_SD_PCI4,
  46         MUX_TYPE_SD_PC_SA_SG_SG,
  47         MUX_TYPE_SD_PC_SA_PC_SG,
  48         MUX_TYPE_SD_PC_SG_SG,
  49 };
  50
  51 enum {
  52         GE0_CLK125,
  53         GE2_CLK125,
  54         GE1_CLK125,
  55 };
  56
  57 int checkboard(void)
  58 {
  59 #ifndef CONFIG_QSPI_BOOT
  60         char buf[64];
  61 #endif
  62 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  63         u8 sw;
  64 #endif
  65
  66         puts("Board: LS1021AQDS\n");
  67
  68 #ifdef CONFIG_SD_BOOT
  69         puts("SD\n");
  70 #elif CONFIG_QSPI_BOOT
  71         puts("QSPI\n");
  72 #else
  73         sw = QIXIS_READ(brdcfg[0]);
  74         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  75
  76         if (sw < 0x8)
  77                 printf("vBank: %d\n", sw);
  78         else if (sw == 0x8)
  79                 puts("PromJet\n");
  80         else if (sw == 0x9)
  81                 puts("NAND\n");
  82         else if (sw == 0x15)
  83                 printf("IFCCard\n");
  84         else
  85                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  86 #endif
  87
  88 #ifndef CONFIG_QSPI_BOOT
  89         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  90                QIXIS_READ(id), QIXIS_READ(arch));
  91
  92         printf("FPGA:  v%d (%s), build %d\n",
  93                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  94                (int)qixis_read_minor());
  95 #endif
  96
  97         return 0;
  98 }
  99
 100 unsigned long get_board_sys_clk(void)
 101 {
 102         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 103
 104         switch (sysclk_conf & 0x0f) {
 105         case QIXIS_SYSCLK_64:
 106                 return 64000000;
 107         case QIXIS_SYSCLK_83:
 108                 return 83333333;
 109         case QIXIS_SYSCLK_100:
 110                 return 100000000;
 111         case QIXIS_SYSCLK_125:
 112                 return 125000000;
 113         case QIXIS_SYSCLK_133:
 114                 return 133333333;
 115         case QIXIS_SYSCLK_150:
 116                 return 150000000;
 117         case QIXIS_SYSCLK_160:
 118                 return 160000000;
 119         case QIXIS_SYSCLK_166:
 120                 return 166666666;
 121         }
 122         return 66666666;
 123 }
 124
 125 unsigned long get_board_ddr_clk(void)
 126 {
 127         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 128
 129         switch ((ddrclk_conf & 0x30) >> 4) {
 130         case QIXIS_DDRCLK_100:
 131                 return 100000000;
 132         case QIXIS_DDRCLK_125:
 133                 return 125000000;
 134         case QIXIS_DDRCLK_133:
 135                 return 133333333;
 136         }
 137         return 66666666;
 138 }
 139
 140 unsigned int get_soc_major_rev(void)
 141 {
 142         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 143         unsigned int svr, major;
 144
 145         svr = in_be32(&gur->svr);
 146         major = SVR_MAJ(svr);
 147
 148         return major;
 149 }
 150
 151 int select_i2c_ch_pca9547(u8 ch)
 152 {
 153         int ret;
 154
 155         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 156         if (ret) {
 157                 puts("PCA: failed to select proper channel\n");
 158                 return ret;
 159         }
 160
 161         return 0;
 162 }
 163
 164 int dram_init(void)
 165 {
 166         /*
 167          * When resuming from deep sleep, the I2C channel may not be
 168          * in the default channel. So, switch to the default channel
 169          * before accessing DDR SPD.
 170          */
 171         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 172         gd->ram_size = initdram(0);
 173
 174         return 0;
 175 }
 176
 177 #ifdef CONFIG_FSL_ESDHC
 178 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 179         {CONFIG_SYS_FSL_ESDHC_ADDR},
 180 };
 181
 182 int board_mmc_init(bd_t *bis)
 183 {
 184         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 185
 186         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 187 }
 188 #endif
 189
 190 int board_early_init_f(void)
 191 {
 192         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 193         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 194         unsigned int major;
 195
 196 #ifdef CONFIG_TSEC_ENET
 197         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 198 #endif
 199
 200 #ifdef CONFIG_FSL_IFC
 201         init_early_memctl_regs();
 202 #endif
 203
 204 #ifdef CONFIG_FSL_QSPI
 205         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 206 #endif
 207
 208 #ifdef CONFIG_FSL_DCU_FB
 209         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 210 #endif
 211
 212         /*
 213          * Enable snoop requests and DVM message requests for
 214          * Slave insterface S4 (A7 core cluster)
 215          */
 216         out_le32(&cci->slave[4].snoop_ctrl,
 217                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 218
 219         major = get_soc_major_rev();
 220         if (major == SOC_MAJOR_VER_1_0) {
 221                 /*
 222                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 223                  * Register All transactions are treated as non-shareable
 224                  */
 225                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 226                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 227
 228                 /* Workaround for the issue that DDR could not respond to
 229                  * barrier transaction which is generated by executing DSB/ISB
 230                  * instruction. Set CCI-400 control override register to
 231                  * terminate the barrier transaction. After DDR is initialized,
 232                  * allow barrier transaction to DDR again */
 233                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 234         }
 235
 236 #if defined(CONFIG_DEEP_SLEEP)
 237         if (is_warm_boot())
 238                 fsl_dp_disable_console();
 239 #endif
 240
 241         return 0;
 242 }
 243
 244 #ifdef CONFIG_SPL_BUILD
 245 void board_init_f(ulong dummy)
 246 {
 247         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 248         unsigned int major;
 249
 250 #ifdef CONFIG_NAND_BOOT
 251         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 252         u32 porsr1, pinctl;
 253
 254         /*
 255          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 256          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 257          * This workaround changes RCW source to make all signals enabled.
 258          */
 259         porsr1 = in_be32(&gur->porsr1);
 260         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 261                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 262         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 263                  pinctl);
 264 #endif
 265
 266         /* Clear the BSS */
 267         memset(__bss_start, 0, __bss_end - __bss_start);
 268
 269 #ifdef CONFIG_FSL_IFC
 270         init_early_memctl_regs();
 271 #endif
 272
 273         get_clocks();
 274
 275 #if defined(CONFIG_DEEP_SLEEP)
 276         if (is_warm_boot())
 277                 fsl_dp_disable_console();
 278 #endif
 279
 280         preloader_console_init();
 281
 282 #ifdef CONFIG_SPL_I2C_SUPPORT
 283         i2c_init_all();
 284 #endif
 285
 286         major = get_soc_major_rev();
 287         if (major == SOC_MAJOR_VER_1_0)
 288                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 289
 290         dram_init();
 291
 292         board_init_r(NULL, 0);
 293 }
 294 #endif
 295
 296 void config_etseccm_source(int etsec_gtx_125_mux)
 297 {
 298         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 299
 300         switch (etsec_gtx_125_mux) {
 301         case GE0_CLK125:
 302                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 303                 debug("etseccm set to GE0_CLK125\n");
 304                 break;
 305
 306         case GE2_CLK125:
 307                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 308                 debug("etseccm set to GE2_CLK125\n");
 309                 break;
 310
 311         case GE1_CLK125:
 312                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 313                 debug("etseccm set to GE1_CLK125\n");
 314                 break;
 315
 316         default:
 317                 printf("Error! trying to set etseccm to invalid value\n");
 318                 break;
 319         }
 320 }
 321
 322 int config_board_mux(int ctrl_type)
 323 {
 324         u8 reg12, reg14;
 325
 326         reg12 = QIXIS_READ(brdcfg[12]);
 327         reg14 = QIXIS_READ(brdcfg[14]);
 328
 329         switch (ctrl_type) {
 330         case MUX_TYPE_CAN:
 331                 config_etseccm_source(GE2_CLK125);
 332                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 333                 break;
 334         case MUX_TYPE_IIC2:
 335                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 336                 break;
 337         case MUX_TYPE_RGMII:
 338                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 339                 break;
 340         case MUX_TYPE_SAI:
 341                 config_etseccm_source(GE2_CLK125);
 342                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 343                 break;
 344         case MUX_TYPE_SDHC:
 345                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 346                 break;
 347         case MUX_TYPE_SD_PCI4:
 348                 reg12 = 0x38;
 349                 break;
 350         case MUX_TYPE_SD_PC_SA_SG_SG:
 351                 reg12 = 0x01;
 352                 break;
 353         case MUX_TYPE_SD_PC_SA_PC_SG:
 354                 reg12 = 0x01;
 355                 break;
 356         case MUX_TYPE_SD_PC_SG_SG:
 357                 reg12 = 0x21;
 358                 break;
 359         default:
 360                 printf("Wrong mux interface type\n");
 361                 return -1;
 362         }
 363
 364         QIXIS_WRITE(brdcfg[12], reg12);
 365         QIXIS_WRITE(brdcfg[14], reg14);
 366
 367         return 0;
 368 }
 369
 370 int config_serdes_mux(void)
 371 {
 372         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 373         u32 cfg;
 374
 375         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 376         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 377
 378         switch (cfg) {
 379         case 0x0:
 380                 config_board_mux(MUX_TYPE_SD_PCI4);
 381                 break;
 382         case 0x30:
 383                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 384                 break;
 385         case 0x60:
 386                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 387                 break;
 388         case 0x70:
 389                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 390                 break;
 391         default:
 392                 printf("SRDS1 prtcl:0x%x\n", cfg);
 393                 break;
 394         }
 395
 396         return 0;
 397 }
 398
 399 int misc_init_r(void)
 400 {
 401         int conflict_flag;
 402
 403         /* some signals can not enable simultaneous*/
 404         conflict_flag = 0;
 405         if (hwconfig("sdhc"))
 406                 conflict_flag++;
 407         if (hwconfig("iic2"))
 408                 conflict_flag++;
 409         if (conflict_flag > 1) {
 410                 printf("WARNING: pin conflict !\n");
 411                 return 0;
 412         }
 413
 414         conflict_flag = 0;
 415         if (hwconfig("rgmii"))
 416                 conflict_flag++;
 417         if (hwconfig("can"))
 418                 conflict_flag++;
 419         if (hwconfig("sai"))
 420                 conflict_flag++;
 421         if (conflict_flag > 1) {
 422                 printf("WARNING: pin conflict !\n");
 423                 return 0;
 424         }
 425
 426         if (hwconfig("can"))
 427                 config_board_mux(MUX_TYPE_CAN);
 428         else if (hwconfig("rgmii"))
 429                 config_board_mux(MUX_TYPE_RGMII);
 430         else if (hwconfig("sai"))
 431                 config_board_mux(MUX_TYPE_SAI);
 432
 433         if (hwconfig("iic2"))
 434                 config_board_mux(MUX_TYPE_IIC2);
 435         else if (hwconfig("sdhc"))
 436                 config_board_mux(MUX_TYPE_SDHC);
 437
 438 #ifdef CONFIG_FSL_CAAM
 439         return sec_init();
 440 #endif
 441         return 0;
 442 }
 443
 444 #ifdef CONFIG_LS102XA_NS_ACCESS
 445 static struct csu_ns_dev ns_dev[] = {
 446         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 447         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 448         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 449         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 450         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 451         { CSU_CSLX_GIC, CSU_ALL_RW },
 452         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 453         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 454         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 455         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 456         { CSU_CSLX_SATA, CSU_ALL_RW },
 457         { CSU_CSLX_USB3, CSU_ALL_RW },
 458         { CSU_CSLX_SERDES, CSU_ALL_RW },
 459         { CSU_CSLX_QDMA, CSU_ALL_RW },
 460         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 461         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 462         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 463         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 464         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 465         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 466         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 467         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 468         { CSU_CSLX_QSPI, CSU_ALL_RW },
 469         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 470         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 471         { CSU_CSLX_IFC, CSU_ALL_RW },
 472         { CSU_CSLX_I2C1, CSU_ALL_RW },
 473         { CSU_CSLX_USB2, CSU_ALL_RW },
 474         { CSU_CSLX_I2C3, CSU_ALL_RW },
 475         { CSU_CSLX_I2C2, CSU_ALL_RW },
 476         { CSU_CSLX_DUART2, CSU_ALL_RW },
 477         { CSU_CSLX_DUART1, CSU_ALL_RW },
 478         { CSU_CSLX_WDT2, CSU_ALL_RW },
 479         { CSU_CSLX_WDT1, CSU_ALL_RW },
 480         { CSU_CSLX_EDMA, CSU_ALL_RW },
 481         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 482         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 483         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 484         { CSU_CSLX_DDR, CSU_ALL_RW },
 485         { CSU_CSLX_QUICC, CSU_ALL_RW },
 486         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 487         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 488         { CSU_CSLX_SFP, CSU_ALL_RW },
 489         { CSU_CSLX_TMU, CSU_ALL_RW },
 490         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 491         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 492         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 493         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 494         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 495         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 496         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 497         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 498         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 499         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 500         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 501         { CSU_CSLX_CSU, CSU_ALL_RW },
 502         { CSU_CSLX_ASRC, CSU_ALL_RW },
 503         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 504         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 505         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 506         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 507         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 508         { CSU_CSLX_SAI2, CSU_ALL_RW },
 509         { CSU_CSLX_SAI1, CSU_ALL_RW },
 510         { CSU_CSLX_SAI4, CSU_ALL_RW },
 511         { CSU_CSLX_SAI3, CSU_ALL_RW },
 512         { CSU_CSLX_FTM2, CSU_ALL_RW },
 513         { CSU_CSLX_FTM1, CSU_ALL_RW },
 514         { CSU_CSLX_FTM4, CSU_ALL_RW },
 515         { CSU_CSLX_FTM3, CSU_ALL_RW },
 516         { CSU_CSLX_FTM6, CSU_ALL_RW },
 517         { CSU_CSLX_FTM5, CSU_ALL_RW },
 518         { CSU_CSLX_FTM8, CSU_ALL_RW },
 519         { CSU_CSLX_FTM7, CSU_ALL_RW },
 520         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 521         { CSU_CSLX_EPU, CSU_ALL_RW },
 522         { CSU_CSLX_GDI, CSU_ALL_RW },
 523         { CSU_CSLX_DDI, CSU_ALL_RW },
 524         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 525         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 526         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 527 };
 528 #endif
 529
 530 struct liodn_id_table sec_liodn_tbl[] = {
 531         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 532         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 533         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 534         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 535         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 536         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 537         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 538         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 539         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 540         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 541         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 542         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 543         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 544         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 545         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 546         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 547 };
 548
 549 struct smmu_stream_id dev_stream_id[] = {
 550         { 0x100, 0x01, "ETSEC MAC1" },
 551         { 0x104, 0x02, "ETSEC MAC2" },
 552         { 0x108, 0x03, "ETSEC MAC3" },
 553         { 0x10c, 0x04, "PEX1" },
 554         { 0x110, 0x05, "PEX2" },
 555         { 0x114, 0x06, "qDMA" },
 556         { 0x118, 0x07, "SATA" },
 557         { 0x11c, 0x08, "USB3" },
 558         { 0x120, 0x09, "QE" },
 559         { 0x124, 0x0a, "eSDHC" },
 560         { 0x128, 0x0b, "eMA" },
 561         { 0x14c, 0x0c, "2D-ACE" },
 562         { 0x150, 0x0d, "USB2" },
 563         { 0x18c, 0x0e, "DEBUG" },
 564 };
 565
 566 int board_init(void)
 567 {
 568         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 569         unsigned int major;
 570
 571         major = get_soc_major_rev();
 572         if (major == SOC_MAJOR_VER_1_0) {
 573                 /* Set CCI-400 control override register to
 574                  * enable barrier transaction */
 575                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 576         }
 577
 578         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 579
 580 #ifndef CONFIG_SYS_FSL_NO_SERDES
 581         fsl_serdes_init();
 582         config_serdes_mux();
 583 #endif
 584
 585         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 586                                       ARRAY_SIZE(sec_liodn_tbl));
 587         ls102xa_config_smmu_stream_id(dev_stream_id,
 588                                       ARRAY_SIZE(dev_stream_id));
 589
 590 #ifdef CONFIG_LS102XA_NS_ACCESS
 591         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 592 #endif
 593
 594 #ifdef CONFIG_U_QE
 595         u_qe_init();
 596 #endif
 597
 598         return 0;
 599 }
 600
 601 #if defined(CONFIG_DEEP_SLEEP)
 602 void board_sleep_prepare(void)
 603 {
 604         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 605         unsigned int major;
 606
 607         major = get_soc_major_rev();
 608         if (major == SOC_MAJOR_VER_1_0) {
 609                 /* Set CCI-400 control override register to
 610                  * enable barrier transaction */
 611                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 612         }
 613
 614
 615 #ifdef CONFIG_LS102XA_NS_ACCESS
 616         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 617 #endif
 618 }
 619 #endif
 620
 621 int ft_board_setup(void *blob, bd_t *bd)
 622 {
 623         ft_cpu_setup(blob, bd);
 624
 625 #ifdef CONFIG_PCI
 626         ft_pci_setup(blob, bd);
 627 #endif
 628
 629         return 0;
 630 }
 631
 632 u8 flash_read8(void *addr)
 633 {
 634         return __raw_readb(addr + 1);
 635 }
 636
 637 void flash_write16(u16 val, void *addr)
 638 {
 639         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 640
 641         __raw_writew(shftval, addr);
 642 }
 643
 644 u16 flash_read16(void *addr)
 645 {
 646         u16 val = __raw_readw(addr);
 647
 648         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 649 }