2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 void fsl_ddr_board_options(memctl_options_t *popts,
16 unsigned int ctrl_num)
18 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 printf("Not supported controller number %d\n", ctrl_num);
30 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
31 * freqency and n_banks specified in board_specific_parameters table.
33 ddr_freq = get_ddr_freq(0) / 1000000;
34 while (pbsp->datarate_mhz_high) {
35 if (pbsp->n_ranks == pdimm->n_ranks) {
36 if (ddr_freq <= pbsp->datarate_mhz_high) {
37 popts->clk_adjust = pbsp->clk_adjust;
38 popts->wrlvl_start = pbsp->wrlvl_start;
39 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
40 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
41 popts->cpo_override = pbsp->cpo_override;
42 popts->write_data_delay =
43 pbsp->write_data_delay;
52 printf("Error: board specific timing not found for %lu MT/s\n",
54 printf("Trying to use the highest speed (%u) parameters\n",
55 pbsp_highest->datarate_mhz_high);
56 popts->clk_adjust = pbsp_highest->clk_adjust;
57 popts->wrlvl_start = pbsp_highest->wrlvl_start;
58 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
59 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
61 panic("DIMM is not supported by this board");
64 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
65 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
67 /* force DDR bus width to 32 bits */
68 popts->data_bus_width = 1;
69 popts->otf_burst_chop_en = 0;
70 popts->burst_length = DDR_BL8;
73 * Factors to consider for half-strength driver enable:
74 * - number of DIMMs installed
76 popts->half_strength_driver_enable = 1;
78 * Write leveling override
80 popts->wrlvl_override = 1;
81 popts->wrlvl_sample = 0xf;
84 * Rtt and Rtt_WR override
86 popts->rtt_override = 0;
88 /* Enable ZQ calibration */
91 #ifdef CONFIG_SYS_FSL_DDR4
92 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
93 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
94 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
96 popts->cswl_override = DDR_CSWL_CS0;
98 /* DHC_EN =1, ODT = 75 Ohm */
99 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
100 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
104 #ifdef CONFIG_SYS_DDR_RAW_TIMING
105 dimm_params_t ddr_raw_timing = {
107 .rank_density = 1073741824u,
108 .capacity = 1073741824u,
109 .primary_sdram_width = 32,
111 .registered_dimm = 0,
115 .n_banks_per_sdram_device = 8,
117 .burst_lengths_bitmask = 0x0c,
120 .caslat_x = 0xfe << 4, /* 5,6,7,8 */
131 .refresh_rate_ps = 7800000,
135 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
136 unsigned int controller_number,
137 unsigned int dimm_number)
139 static const char dimm_model[] = "Fixed DDR on board";
141 if (((controller_number == 0) && (dimm_number == 0)) ||
142 ((controller_number == 1) && (dimm_number == 0))) {
143 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
144 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
145 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
152 phys_size_t initdram(int board_type)
154 phys_size_t dram_size;
156 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
157 puts("Initializing DDR....using SPD\n");
158 dram_size = fsl_ddr_sdram();
160 dram_size = fsl_ddr_sdram_size();
165 void dram_init_banksize(void)
167 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
168 gd->bd->bi_dram[0].size = gd->ram_size;