2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
18 #include <fsl_esdhc.h>
19 #include <environment.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
31 while (in_be32(ptr) & bits) {
36 puts("Error: wait for clear timeout.\n");
43 puts("Board: LS1012ARDB ");
45 /* Initialize i2c early for Serial flash bank information */
48 if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
49 printf("Error reading i2c boot information!\n");
50 return 0; /* Don't want to hang() on this error */
54 if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
56 else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
61 printf(", boot from QSPI");
62 if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
64 else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
66 else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
76 struct mmdc_p_regs *mmdc =
77 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
79 out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
81 /* configure timing parms */
82 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
83 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
84 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
85 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
88 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
89 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
90 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
91 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
93 /* out of reset delays */
94 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
97 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
98 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
101 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
103 /* dram init sequence: update MRs */
104 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
105 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
106 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
108 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
109 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
110 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
111 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
112 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
114 /* dram init sequence: ZQCL */
115 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
116 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
117 set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
118 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
119 FORCE_ZQ_AUTO_CALIBRATION);
121 /* Calibrations now: wr lvl */
122 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
123 CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
125 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
126 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
130 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
131 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
132 out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
136 /* Calibrations now: Read DQS gating calibration */
137 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
138 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
139 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
140 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
141 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
142 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
143 set_wait_for_bits_clear(&mmdc->mpdgctrl0,
144 AUTO_RD_DQS_GATING_CALIBRATION_EN,
145 AUTO_RD_DQS_GATING_CALIBRATION_EN);
147 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
150 /* Calibrations now: Read calibration */
151 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
152 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
153 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
154 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
155 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
156 set_wait_for_bits_clear(&mmdc->mprddlhwctl,
157 AUTO_RD_CALIBRATION_EN,
158 AUTO_RD_CALIBRATION_EN);
160 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
164 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
165 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
168 set_wait_for_bits_clear(&mmdc->mdref,
169 CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
172 /* disable CON_REQ */
173 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
180 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
185 int board_eth_init(bd_t *bis)
187 return pci_eth_init(bis);
190 int board_early_init_f(void)
192 fsl_lsch2_early_init_f();
199 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
201 * Set CCI-400 control override register to enable barrier
204 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
206 #ifdef CONFIG_ENV_IS_NOWHERE
207 gd->env_addr = (ulong)&default_environment[0];
210 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
211 enable_layerscape_ns_access();
217 int ft_board_setup(void *blob, bd_t *bd)
219 arch_fixup_fdt(blob);
221 ft_cpu_setup(blob, bd);