board/freescale/ls1012aqds/ls1012aqds.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #ifdef CONFIG_FSL_LS_PPA
  14 #include <asm/arch/ppa.h>
  15 #endif
  16 #include <asm/arch/fdt.h>
  17 #include <asm/arch/soc.h>
  18 #include <ahci.h>
  19 #include <hwconfig.h>
  20 #include <mmc.h>
  21 #include <scsi.h>
  22 #include <fm_eth.h>
  23 #include <fsl_esdhc.h>
  24 #include <fsl_mmdc.h>
  25 #include <spl.h>
  26 #include <netdev.h>
  27
  28 #include "../common/qixis.h"
  29 #include "ls1012aqds_qixis.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int checkboard(void)
  34 {
  35         char buf[64];
  36         u8 sw;
  37
  38         sw = QIXIS_READ(arch);
  39         printf("Board Arch: V%d, ", sw >> 4);
  40         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  41
  42         sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  43
  44         if (sw & QIXIS_LBMAP_ALTBANK)
  45                 printf("flash: 2\n");
  46         else
  47                 printf("flash: 1\n");
  48
  49         printf("FPGA: v%d (%s), build %d",
  50                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  51                (int)qixis_read_minor());
  52
  53         /* the timestamp string contains "\n" at the end */
  54         printf(" on %s", qixis_read_time(buf));
  55         return 0;
  56 }
  57
  58 int dram_init(void)
  59 {
  60         static const struct fsl_mmdc_info mparam = {
  61                 0x05180000,     /* mdctl */
  62                 0x00030035,     /* mdpdc */
  63                 0x12554000,     /* mdotc */
  64                 0xbabf7954,     /* mdcfg0 */
  65                 0xdb328f64,     /* mdcfg1 */
  66                 0x01ff00db,     /* mdcfg2 */
  67                 0x00001680,     /* mdmisc */
  68                 0x0f3c8000,     /* mdref */
  69                 0x00002000,     /* mdrwd */
  70                 0x00bf1023,     /* mdor */
  71                 0x0000003f,     /* mdasp */
  72                 0x0000022a,     /* mpodtctrl */
  73                 0xa1390003,     /* mpzqhwctrl */
  74         };
  75
  76         mmdc_init(&mparam);
  77
  78         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  79
  80         return 0;
  81 }
  82
  83 int board_early_init_f(void)
  84 {
  85         fsl_lsch2_early_init_f();
  86
  87         return 0;
  88 }
  89
  90 #ifdef CONFIG_MISC_INIT_R
  91 int misc_init_r(void)
  92 {
  93         u8 mux_sdhc_cd = 0x80;
  94
  95         i2c_set_bus_num(0);
  96
  97         i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
  98         return 0;
  99 }
 100 #endif
 101
 102 int board_init(void)
 103 {
 104         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
 105                                    CONFIG_SYS_CCI400_ADDR;
 106
 107         /* Set CCI-400 control override register to enable barrier
 108          * transaction */
 109         out_le32(&cci->ctrl_ord,
 110                  CCI400_CTRLORD_EN_BARRIER);
 111
 112 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 113         erratum_a010315();
 114 #endif
 115
 116 #ifdef CONFIG_ENV_IS_NOWHERE
 117         gd->env_addr = (ulong)&default_environment[0];
 118 #endif
 119
 120 #ifdef CONFIG_FSL_LS_PPA
 121         ppa_init();
 122 #endif
 123         return 0;
 124 }
 125
 126 int board_eth_init(bd_t *bis)
 127 {
 128         return pci_eth_init(bis);
 129 }
 130
 131 int esdhc_status_fixup(void *blob, const char *compat)
 132 {
 133         char esdhc0_path[] = "/soc/esdhc@1560000";
 134         char esdhc1_path[] = "/soc/esdhc@1580000";
 135         u8 card_id;
 136
 137         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 138                          sizeof("okay"), 1);
 139
 140         /*
 141          * The Presence Detect 2 register detects the installation
 142          * of cards in various PCI Express or SGMII slots.
 143          *
 144          * STAT_PRS2[7:5]: Specifies the type of card installed in the
 145          * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
 146          */
 147         card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
 148
 149         /* If no adapter is installed in SDHC2, disable SDHC2 */
 150         if (card_id == 0x7)
 151                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 152                                  sizeof("disabled"), 1);
 153         else
 154                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 155                                  sizeof("okay"), 1);
 156         return 0;
 157 }
 158
 159 #ifdef CONFIG_OF_BOARD_SETUP
 160 int ft_board_setup(void *blob, bd_t *bd)
 161 {
 162         arch_fixup_fdt(blob);
 163
 164         ft_cpu_setup(blob, bd);
 165
 166         return 0;
 167 }
 168 #endif
 169
 170 void dram_init_banksize(void)
 171 {
 172         /*
 173          * gd->arch.secure_ram tracks the location of secure memory.
 174          * It was set as if the memory starts from 0.
 175          * The address needs to add the offset of its bank.
 176          */
 177         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 178         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 179                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 180                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 181                 gd->bd->bi_dram[1].size = gd->ram_size -
 182                         CONFIG_SYS_DDR_BLOCK1_SIZE;
 183 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 184                 gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 185                         gd->arch.secure_ram -
 186                         CONFIG_SYS_DDR_BLOCK1_SIZE;
 187                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 188 #endif
 189         } else {
 190                 gd->bd->bi_dram[0].size = gd->ram_size;
 191 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 192                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 193                         gd->arch.secure_ram;
 194                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 195 #endif
 196         }
 197 }