2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_FSL_LS_PPA
14 #include <asm/arch/ppa.h>
16 #include <asm/arch/fdt.h>
17 #include <asm/arch/mmu.h>
18 #include <asm/arch/soc.h>
24 #include <fsl_esdhc.h>
29 #include "../common/qixis.h"
30 #include "ls1012aqds_qixis.h"
32 DECLARE_GLOBAL_DATA_PTR;
39 sw = QIXIS_READ(arch);
40 printf("Board Arch: V%d, ", sw >> 4);
41 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
43 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
45 if (sw & QIXIS_LBMAP_ALTBANK)
50 printf("FPGA: v%d (%s), build %d",
51 (int)QIXIS_READ(scver), qixis_read_tag(buf),
52 (int)qixis_read_minor());
54 /* the timestamp string contains "\n" at the end */
55 printf(" on %s", qixis_read_time(buf));
61 static const struct fsl_mmdc_info mparam = {
62 0x05180000, /* mdctl */
63 0x00030035, /* mdpdc */
64 0x12554000, /* mdotc */
65 0xbabf7954, /* mdcfg0 */
66 0xdb328f64, /* mdcfg1 */
67 0x01ff00db, /* mdcfg2 */
68 0x00001680, /* mdmisc */
69 0x0f3c8000, /* mdref */
70 0x00002000, /* mdrwd */
71 0x00bf1023, /* mdor */
72 0x0000003f, /* mdasp */
73 0x0000022a, /* mpodtctrl */
74 0xa1390003, /* mpzqhwctrl */
79 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
80 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
81 /* This will break-before-make MMU for DDR */
82 update_early_mmu_table();
88 int board_early_init_f(void)
90 fsl_lsch2_early_init_f();
95 #ifdef CONFIG_MISC_INIT_R
98 u8 mux_sdhc_cd = 0x80;
102 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
109 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
110 CONFIG_SYS_CCI400_ADDR;
112 /* Set CCI-400 control override register to enable barrier
114 out_le32(&cci->ctrl_ord,
115 CCI400_CTRLORD_EN_BARRIER);
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
121 #ifdef CONFIG_ENV_IS_NOWHERE
122 gd->env_addr = (ulong)&default_environment[0];
125 #ifdef CONFIG_FSL_LS_PPA
131 int board_eth_init(bd_t *bis)
133 return pci_eth_init(bis);
136 int esdhc_status_fixup(void *blob, const char *compat)
138 char esdhc0_path[] = "/soc/esdhc@1560000";
139 char esdhc1_path[] = "/soc/esdhc@1580000";
142 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
146 * The Presence Detect 2 register detects the installation
147 * of cards in various PCI Express or SGMII slots.
149 * STAT_PRS2[7:5]: Specifies the type of card installed in the
150 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
152 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
154 /* If no adapter is installed in SDHC2, disable SDHC2 */
156 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
157 sizeof("disabled"), 1);
159 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
164 #ifdef CONFIG_OF_BOARD_SETUP
165 int ft_board_setup(void *blob, bd_t *bd)
167 arch_fixup_fdt(blob);
169 ft_cpu_setup(blob, bd);