1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #ifdef CONFIG_FSL_LS_PPA
13 #include <asm/arch/ppa.h>
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/mmu.h>
17 #include <asm/arch/soc.h>
21 #include <env_internal.h>
24 #include <fsl_esdhc.h>
29 #include "../common/qixis.h"
30 #include "ls1012aqds_qixis.h"
31 #include "ls1012aqds_pfe.h"
33 DECLARE_GLOBAL_DATA_PTR;
40 sw = QIXIS_READ(arch);
41 printf("Board Arch: V%d, ", sw >> 4);
42 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
44 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
46 if (sw & QIXIS_LBMAP_ALTBANK)
51 printf("FPGA: v%d (%s), build %d",
52 (int)QIXIS_READ(scver), qixis_read_tag(buf),
53 (int)qixis_read_minor());
55 /* the timestamp string contains "\n" at the end */
56 printf(" on %s", qixis_read_time(buf));
63 gd->ram_size = tfa_get_dram_size();
65 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
72 static const struct fsl_mmdc_info mparam = {
73 0x05180000, /* mdctl */
74 0x00030035, /* mdpdc */
75 0x12554000, /* mdotc */
76 0xbabf7954, /* mdcfg0 */
77 0xdb328f64, /* mdcfg1 */
78 0x01ff00db, /* mdcfg2 */
79 0x00001680, /* mdmisc */
80 0x0f3c8000, /* mdref */
81 0x00002000, /* mdrwd */
82 0x00bf1023, /* mdor */
83 0x0000003f, /* mdasp */
84 0x0000022a, /* mpodtctrl */
85 0xa1390003, /* mpzqhwctrl */
89 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
90 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
91 /* This will break-before-make MMU for DDR */
92 update_early_mmu_table();
99 int board_early_init_f(void)
101 fsl_lsch2_early_init_f();
106 #ifdef CONFIG_MISC_INIT_R
107 int misc_init_r(void)
109 u8 mux_sdhc_cd = 0x80;
113 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
120 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
121 CONFIG_SYS_CCI400_OFFSET);
123 /* Set CCI-400 control override register to enable barrier
125 if (current_el() == 3)
126 out_le32(&cci->ctrl_ord,
127 CCI400_CTRLORD_EN_BARRIER);
129 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
133 #ifdef CONFIG_ENV_IS_NOWHERE
134 gd->env_addr = (ulong)&default_environment[0];
137 #ifdef CONFIG_FSL_CAAM
141 #ifdef CONFIG_FSL_LS_PPA
147 int esdhc_status_fixup(void *blob, const char *compat)
149 char esdhc0_path[] = "/soc/esdhc@1560000";
150 char esdhc1_path[] = "/soc/esdhc@1580000";
153 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
157 * The Presence Detect 2 register detects the installation
158 * of cards in various PCI Express or SGMII slots.
160 * STAT_PRS2[7:5]: Specifies the type of card installed in the
161 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
163 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
165 /* If no adapter is installed in SDHC2, disable SDHC2 */
167 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
168 sizeof("disabled"), 1);
170 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
175 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
176 char *enet_path, char *mdio_path)
178 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
179 &prop_val.busid, PFE_PROP_LEN, 1);
180 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
181 &prop_val.phyid, PFE_PROP_LEN, 1);
182 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
183 &prop_val.mux_val, PFE_PROP_LEN, 1);
184 do_fixup_by_path(set_blob, enet_path, "phy-mode",
185 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
186 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
187 &prop_val.phy_mask, PFE_PROP_LEN, 1);
191 static void fdt_fsl_fixup_of_pfe(void *blob)
194 struct pfe_prop_val prop_val;
197 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
198 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
199 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
200 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
202 for (i = 0; i < NUM_ETH_NODE; i++) {
204 case SERDES_1_G_PROTOCOL:
206 prop_val.busid = cpu_to_fdt32(
208 prop_val.phyid = cpu_to_fdt32(
210 prop_val.mux_val = cpu_to_fdt32(
212 prop_val.phy_mask = cpu_to_fdt32(
213 ETH_1G_MDIO_PHY_MASK);
214 prop_val.phy_mode = "sgmii";
215 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
218 prop_val.busid = cpu_to_fdt32(
220 prop_val.phyid = cpu_to_fdt32(
222 prop_val.mux_val = cpu_to_fdt32(
224 prop_val.phy_mask = cpu_to_fdt32(
225 ETH_1G_MDIO_PHY_MASK);
226 prop_val.phy_mode = "rgmii";
227 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
231 case SERDES_2_5_G_PROTOCOL:
233 prop_val.busid = cpu_to_fdt32(
235 prop_val.phyid = cpu_to_fdt32(
237 prop_val.mux_val = cpu_to_fdt32(
238 ETH_1_2_5G_MDIO_MUX);
239 prop_val.phy_mask = cpu_to_fdt32(
240 ETH_2_5G_MDIO_PHY_MASK);
241 prop_val.phy_mode = "sgmii-2500";
242 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
245 prop_val.busid = cpu_to_fdt32(
247 prop_val.phyid = cpu_to_fdt32(
249 prop_val.mux_val = cpu_to_fdt32(
250 ETH_2_2_5G_MDIO_MUX);
251 prop_val.phy_mask = cpu_to_fdt32(
252 ETH_2_5G_MDIO_PHY_MASK);
253 prop_val.phy_mode = "sgmii-2500";
254 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
259 printf("serdes:[%d]\n", srds_s1);
264 #ifdef CONFIG_OF_BOARD_SETUP
265 int ft_board_setup(void *blob, bd_t *bd)
267 arch_fixup_fdt(blob);
269 ft_cpu_setup(blob, bd);
270 fdt_fsl_fixup_of_pfe(blob);