board/freescale/ls1012aqds/ls1012aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <fdt_support.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #ifdef CONFIG_FSL_LS_PPA
  13 #include <asm/arch/ppa.h>
  14 #endif
  15 #include <asm/arch/fdt.h>
  16 #include <asm/arch/mmu.h>
  17 #include <asm/arch/soc.h>
  18 #include <ahci.h>
  19 #include <hwconfig.h>
  20 #include <mmc.h>
  21 #include <env_internal.h>
  22 #include <scsi.h>
  23 #include <fm_eth.h>
  24 #include <fsl_esdhc.h>
  25 #include <fsl_mmdc.h>
  26 #include <spl.h>
  27 #include <netdev.h>
  28 #include <fsl_sec.h>
  29 #include "../common/qixis.h"
  30 #include "ls1012aqds_qixis.h"
  31 #include "ls1012aqds_pfe.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 int checkboard(void)
  36 {
  37         char buf[64];
  38         u8 sw;
  39
  40         sw = QIXIS_READ(arch);
  41         printf("Board Arch: V%d, ", sw >> 4);
  42         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  43
  44         sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  45
  46         if (sw & QIXIS_LBMAP_ALTBANK)
  47                 printf("flash: 2\n");
  48         else
  49                 printf("flash: 1\n");
  50
  51         printf("FPGA: v%d (%s), build %d",
  52                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  53                (int)qixis_read_minor());
  54
  55         /* the timestamp string contains "\n" at the end */
  56         printf(" on %s", qixis_read_time(buf));
  57         return 0;
  58 }
  59
  60 #ifdef CONFIG_TFABOOT
  61 int dram_init(void)
  62 {
  63         gd->ram_size = tfa_get_dram_size();
  64         if (!gd->ram_size)
  65                 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  66
  67         return 0;
  68 }
  69 #else
  70 int dram_init(void)
  71 {
  72         static const struct fsl_mmdc_info mparam = {
  73                 0x05180000,     /* mdctl */
  74                 0x00030035,     /* mdpdc */
  75                 0x12554000,     /* mdotc */
  76                 0xbabf7954,     /* mdcfg0 */
  77                 0xdb328f64,     /* mdcfg1 */
  78                 0x01ff00db,     /* mdcfg2 */
  79                 0x00001680,     /* mdmisc */
  80                 0x0f3c8000,     /* mdref */
  81                 0x00002000,     /* mdrwd */
  82                 0x00bf1023,     /* mdor */
  83                 0x0000003f,     /* mdasp */
  84                 0x0000022a,     /* mpodtctrl */
  85                 0xa1390003,     /* mpzqhwctrl */
  86         };
  87
  88         mmdc_init(&mparam);
  89         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  90 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  91         /* This will break-before-make MMU for DDR */
  92         update_early_mmu_table();
  93 #endif
  94
  95         return 0;
  96 }
  97 #endif
  98
  99 int board_early_init_f(void)
 100 {
 101         fsl_lsch2_early_init_f();
 102
 103         return 0;
 104 }
 105
 106 #ifdef CONFIG_MISC_INIT_R
 107 int misc_init_r(void)
 108 {
 109         u8 mux_sdhc_cd = 0x80;
 110
 111         i2c_set_bus_num(0);
 112
 113         i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 114         return 0;
 115 }
 116 #endif
 117
 118 int board_init(void)
 119 {
 120         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 121                                    CONFIG_SYS_CCI400_OFFSET);
 122
 123         /* Set CCI-400 control override register to enable barrier
 124          * transaction */
 125         if (current_el() == 3)
 126                 out_le32(&cci->ctrl_ord,
 127                          CCI400_CTRLORD_EN_BARRIER);
 128
 129 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 130         erratum_a010315();
 131 #endif
 132
 133 #ifdef CONFIG_ENV_IS_NOWHERE
 134         gd->env_addr = (ulong)&default_environment[0];
 135 #endif
 136
 137 #ifdef CONFIG_FSL_CAAM
 138         sec_init();
 139 #endif
 140
 141 #ifdef CONFIG_FSL_LS_PPA
 142         ppa_init();
 143 #endif
 144         return 0;
 145 }
 146
 147 int esdhc_status_fixup(void *blob, const char *compat)
 148 {
 149         char esdhc0_path[] = "/soc/esdhc@1560000";
 150         char esdhc1_path[] = "/soc/esdhc@1580000";
 151         u8 card_id;
 152
 153         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 154                          sizeof("okay"), 1);
 155
 156         /*
 157          * The Presence Detect 2 register detects the installation
 158          * of cards in various PCI Express or SGMII slots.
 159          *
 160          * STAT_PRS2[7:5]: Specifies the type of card installed in the
 161          * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
 162          */
 163         card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
 164
 165         /* If no adapter is installed in SDHC2, disable SDHC2 */
 166         if (card_id == 0x7)
 167                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 168                                  sizeof("disabled"), 1);
 169         else
 170                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 171                                  sizeof("okay"), 1);
 172         return 0;
 173 }
 174
 175 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
 176                               char *enet_path, char *mdio_path)
 177 {
 178         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
 179                          &prop_val.busid, PFE_PROP_LEN, 1);
 180         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
 181                          &prop_val.phyid, PFE_PROP_LEN, 1);
 182         do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
 183                          &prop_val.mux_val, PFE_PROP_LEN, 1);
 184         do_fixup_by_path(set_blob, enet_path, "phy-mode",
 185                          prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
 186         do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
 187                          &prop_val.phy_mask, PFE_PROP_LEN, 1);
 188         return 0;
 189 }
 190
 191 static void fdt_fsl_fixup_of_pfe(void *blob)
 192 {
 193         int i = 0;
 194         struct pfe_prop_val prop_val;
 195         void *l_blob = blob;
 196
 197         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 198         unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
 199                 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 200         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 201
 202         for (i = 0; i < NUM_ETH_NODE; i++) {
 203                 switch (srds_s1) {
 204                 case SERDES_1_G_PROTOCOL:
 205                         if (i == 0) {
 206                                 prop_val.busid = cpu_to_fdt32(
 207                                                 ETH_1_1G_BUS_ID);
 208                                 prop_val.phyid = cpu_to_fdt32(
 209                                                 ETH_1_1G_PHY_ID);
 210                                 prop_val.mux_val = cpu_to_fdt32(
 211                                                 ETH_1_1G_MDIO_MUX);
 212                                 prop_val.phy_mask = cpu_to_fdt32(
 213                                                 ETH_1G_MDIO_PHY_MASK);
 214                                 prop_val.phy_mode = "sgmii";
 215                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 216                                                    ETH_1_MDIO);
 217                         } else {
 218                                 prop_val.busid = cpu_to_fdt32(
 219                                                 ETH_2_1G_BUS_ID);
 220                                 prop_val.phyid = cpu_to_fdt32(
 221                                                 ETH_2_1G_PHY_ID);
 222                                 prop_val.mux_val = cpu_to_fdt32(
 223                                                 ETH_2_1G_MDIO_MUX);
 224                                 prop_val.phy_mask = cpu_to_fdt32(
 225                                                 ETH_1G_MDIO_PHY_MASK);
 226                                 prop_val.phy_mode = "rgmii";
 227                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 228                                                    ETH_2_MDIO);
 229                         }
 230                 break;
 231                 case SERDES_2_5_G_PROTOCOL:
 232                         if (i == 0) {
 233                                 prop_val.busid = cpu_to_fdt32(
 234                                                 ETH_1_2_5G_BUS_ID);
 235                                 prop_val.phyid = cpu_to_fdt32(
 236                                                 ETH_1_2_5G_PHY_ID);
 237                                 prop_val.mux_val = cpu_to_fdt32(
 238                                                 ETH_1_2_5G_MDIO_MUX);
 239                                 prop_val.phy_mask = cpu_to_fdt32(
 240                                                 ETH_2_5G_MDIO_PHY_MASK);
 241                                 prop_val.phy_mode = "sgmii-2500";
 242                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 243                                                    ETH_1_MDIO);
 244                         } else {
 245                                 prop_val.busid = cpu_to_fdt32(
 246                                                 ETH_2_2_5G_BUS_ID);
 247                                 prop_val.phyid = cpu_to_fdt32(
 248                                                 ETH_2_2_5G_PHY_ID);
 249                                 prop_val.mux_val = cpu_to_fdt32(
 250                                                 ETH_2_2_5G_MDIO_MUX);
 251                                 prop_val.phy_mask = cpu_to_fdt32(
 252                                                 ETH_2_5G_MDIO_PHY_MASK);
 253                                 prop_val.phy_mode = "sgmii-2500";
 254                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 255                                                    ETH_2_MDIO);
 256                         }
 257                 break;
 258                 default:
 259                         printf("serdes:[%d]\n", srds_s1);
 260                 }
 261         }
 262 }
 263
 264 #ifdef CONFIG_OF_BOARD_SETUP
 265 int ft_board_setup(void *blob, bd_t *bd)
 266 {
 267         arch_fixup_fdt(blob);
 268
 269         ft_cpu_setup(blob, bd);
 270         fdt_fsl_fixup_of_pfe(blob);
 271
 272         return 0;
 273 }
 274 #endif