1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
14 #include <asm/types.h>
15 #include <fsl_dtsec.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch-fsl-layerscape/config.h>
18 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include "../common/qixis.h"
21 #include <net/pfe_eth/pfe_eth.h>
22 #include <dm/platform_data/pfe_dm_eth.h>
23 #include "ls1012aqds_qixis.h"
30 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
31 #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
33 static const char * const mdio_names[] = {
35 "LS1012AQDS_MDIO_RGMII",
36 "LS1012AQDS_MDIO_SLOT1",
37 "LS1012AQDS_MDIO_SLOT2",
41 static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
43 return mdio_names[muxval];
46 struct ls1012aqds_mdio {
48 struct mii_dev *realbus;
51 static void ls1012aqds_mux_mdio(u8 muxval)
56 brdcfg4 = QIXIS_READ(brdcfg[4]);
57 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
58 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
59 QIXIS_WRITE(brdcfg[4], brdcfg4);
63 static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
66 struct ls1012aqds_mdio *priv = bus->priv;
68 ls1012aqds_mux_mdio(priv->muxval);
70 return priv->realbus->read(priv->realbus, addr, devad, regnum);
73 static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
74 int regnum, u16 value)
76 struct ls1012aqds_mdio *priv = bus->priv;
78 ls1012aqds_mux_mdio(priv->muxval);
80 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
83 static int ls1012aqds_mdio_reset(struct mii_dev *bus)
85 struct ls1012aqds_mdio *priv = bus->priv;
87 if (priv->realbus->reset)
88 return priv->realbus->reset(priv->realbus);
93 static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
95 struct ls1012aqds_mdio *pmdio;
96 struct mii_dev *bus = mdio_alloc();
99 printf("Failed to allocate ls1012aqds MDIO bus\n");
103 pmdio = malloc(sizeof(*pmdio));
105 printf("Failed to allocate ls1012aqds private data\n");
110 bus->read = ls1012aqds_mdio_read;
111 bus->write = ls1012aqds_mdio_write;
112 bus->reset = ls1012aqds_mdio_reset;
113 sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
115 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
117 if (!pmdio->realbus) {
118 printf("No bus with name %s\n", realbusname);
124 pmdio->muxval = muxval;
126 return mdio_register(bus);
129 int pfe_eth_board_init(struct udevice *dev)
131 static int init_done;
133 static const char *mdio_name;
134 struct pfe_mdio_info mac_mdio_info;
135 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
137 struct pfe_eth_dev *priv = dev_get_priv(dev);
139 int srds_s1 = in_be32(&gur->rcwsr[4]) &
140 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
141 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
143 ls1012aqds_mux_mdio(EMI1_SLOT1);
146 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
147 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
149 bus = pfe_mdio_init(&mac_mdio_info);
151 printf("Failed to register mdio\n");
157 if (priv->gemac_port) {
158 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
159 mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
161 bus = pfe_mdio_init(&mac_mdio_info);
163 printf("Failed to register mdio\n");
170 printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
171 #ifdef CONFIG_PFE_RGMII_RESET_WA
173 * Work around for FPGA registers initialization
174 * This is needed for RGMII to work.
176 printf("Reset RGMII WA....\n");
177 data8 = QIXIS_READ(rst_frc[0]);
179 QIXIS_WRITE(rst_frc[0], data8);
180 data8 = QIXIS_READ(rst_frc[0]);
182 data8 = QIXIS_READ(res8[6]);
184 QIXIS_WRITE(res8[6], data8);
185 data8 = QIXIS_READ(res8[6]);
187 if (priv->gemac_port) {
188 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
189 if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
191 printf("Failed to register mdio for %s\n", mdio_name);
195 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
196 bus = miiphy_get_dev_by_name(mdio_name);
197 pfe_set_mdio(priv->gemac_port, bus);
198 pfe_set_phy_address_mode(priv->gemac_port,
199 CONFIG_PFE_EMAC2_PHY_ADDR,
200 PHY_INTERFACE_MODE_RGMII);
203 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
204 if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
206 printf("Failed to register mdio for %s\n", mdio_name);
210 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
211 bus = miiphy_get_dev_by_name(mdio_name);
212 pfe_set_mdio(priv->gemac_port, bus);
213 pfe_set_phy_address_mode(priv->gemac_port,
214 CONFIG_PFE_EMAC1_PHY_ADDR,
215 PHY_INTERFACE_MODE_SGMII);
221 printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
223 * Work around for FPGA registers initialization
224 * This is needed for RGMII to work.
226 printf("Reset SLOT1 SLOT2....\n");
227 data8 = QIXIS_READ(rst_frc[2]);
229 QIXIS_WRITE(rst_frc[2], data8);
231 data8 = QIXIS_READ(rst_frc[2]);
233 QIXIS_WRITE(rst_frc[2], data8);
235 if (priv->gemac_port) {
236 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
237 if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
239 printf("Failed to register mdio for %s\n", mdio_name);
242 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
243 bus = miiphy_get_dev_by_name(mdio_name);
244 pfe_set_mdio(1, bus);
245 pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
246 PHY_INTERFACE_MODE_SGMII_2500);
248 data8 = QIXIS_READ(brdcfg[12]);
250 QIXIS_WRITE(brdcfg[12], data8);
253 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
254 if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
256 printf("Failed to register mdio for %s\n", mdio_name);
260 mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
261 bus = miiphy_get_dev_by_name(mdio_name);
262 pfe_set_mdio(0, bus);
263 pfe_set_phy_address_mode(0,
264 CONFIG_PFE_SGMII_2500_PHY1_ADDR,
265 PHY_INTERFACE_MODE_SGMII_2500);
270 printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
276 static struct pfe_eth_pdata pfe_pdata0 = {
277 .pfe_eth_pdata_mac = {
278 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
283 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
284 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
288 static struct pfe_eth_pdata pfe_pdata1 = {
289 .pfe_eth_pdata_mac = {
290 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
295 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
296 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
300 U_BOOT_DEVICE(ls1012a_pfe0) = {
302 .platdata = &pfe_pdata0,
305 U_BOOT_DEVICE(ls1012a_pfe1) = {
307 .platdata = &pfe_pdata1,