board/freescale/ls1012afrdm/ls1012afrdm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #ifdef CONFIG_FSL_LS_PPA
  12 #include <asm/arch/ppa.h>
  13 #endif
  14 #include <asm/arch/mmu.h>
  15 #include <asm/arch/soc.h>
  16 #include <fsl_esdhc.h>
  17 #include <hwconfig.h>
  18 #include <environment.h>
  19 #include <fsl_mmdc.h>
  20 #include <netdev.h>
  21 #include <fsl_sec.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static inline int get_board_version(void)
  26 {
  27         uint32_t val;
  28 #ifdef CONFIG_TARGET_LS1012AFRDM
  29         val = 0;
  30 #else
  31         struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  32
  33         val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
  34
  35 #endif
  36         return val;
  37 }
  38
  39 int checkboard(void)
  40 {
  41 #ifdef CONFIG_TARGET_LS1012AFRDM
  42         puts("Board: LS1012AFRDM ");
  43 #else
  44         int rev;
  45
  46         rev = get_board_version();
  47
  48         puts("Board: FRWY-LS1012A ");
  49
  50         puts("Version");
  51
  52         switch (rev) {
  53         case BOARD_REV_A_B:
  54                 puts(": RevA/B ");
  55                 break;
  56         case BOARD_REV_C:
  57                 puts(": RevC ");
  58                 break;
  59         default:
  60                 puts(": unknown");
  61                 break;
  62         }
  63 #endif
  64
  65         return 0;
  66 }
  67
  68 #ifdef CONFIG_TARGET_LS1012AFRWY
  69 int esdhc_status_fixup(void *blob, const char *compat)
  70 {
  71         char esdhc0_path[] = "/soc/esdhc@1560000";
  72         char esdhc1_path[] = "/soc/esdhc@1580000";
  73
  74         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  75                          sizeof("okay"), 1);
  76
  77         do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  78                          sizeof("disabled"), 1);
  79         return 0;
  80 }
  81 #endif
  82
  83 #ifdef CONFIG_TFABOOT
  84 int dram_init(void)
  85 {
  86 #ifdef CONFIG_TARGET_LS1012AFRWY
  87         int board_rev;
  88 #endif
  89
  90         gd->ram_size = tfa_get_dram_size();
  91
  92         if (!gd->ram_size) {
  93 #ifdef CONFIG_TARGET_LS1012AFRWY
  94                 board_rev = get_board_version();
  95
  96                 if (board_rev & BOARD_REV_C)
  97                         gd->ram_size = SYS_SDRAM_SIZE_1024;
  98                 else
  99                         gd->ram_size = SYS_SDRAM_SIZE_512;
 100 #else
 101                 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 102 #endif
 103         }
 104         return 0;
 105 }
 106 #else
 107 int dram_init(void)
 108 {
 109 #ifdef CONFIG_TARGET_LS1012AFRWY
 110         int board_rev;
 111 #endif
 112         struct fsl_mmdc_info mparam = {
 113                 0x04180000,     /* mdctl */
 114                 0x00030035,     /* mdpdc */
 115                 0x12554000,     /* mdotc */
 116                 0xbabf7954,     /* mdcfg0 */
 117                 0xdb328f64,     /* mdcfg1 */
 118                 0x01ff00db,     /* mdcfg2 */
 119                 0x00001680,     /* mdmisc */
 120                 0x0f3c8000,     /* mdref */
 121                 0x00002000,     /* mdrwd */
 122                 0x00bf1023,     /* mdor */
 123                 0x0000003f,     /* mdasp */
 124                 0x0000022a,     /* mpodtctrl */
 125                 0xa1390003,     /* mpzqhwctrl */
 126         };
 127
 128 #ifdef CONFIG_TARGET_LS1012AFRWY
 129         board_rev = get_board_version();
 130
 131         if (board_rev == BOARD_REV_C) {
 132                 mparam.mdctl = 0x05180000;
 133                 gd->ram_size = SYS_SDRAM_SIZE_1024;
 134         } else {
 135                 gd->ram_size = SYS_SDRAM_SIZE_512;
 136         }
 137 #else
 138         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 139 #endif
 140         mmdc_init(&mparam);
 141
 142 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 143         /* This will break-before-make MMU for DDR */
 144         update_early_mmu_table();
 145 #endif
 146
 147         return 0;
 148 }
 149 #endif
 150
 151 int board_early_init_f(void)
 152 {
 153         fsl_lsch2_early_init_f();
 154
 155         return 0;
 156 }
 157
 158 int board_init(void)
 159 {
 160         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 161                                         CONFIG_SYS_CCI400_OFFSET);
 162
 163         /*
 164          * Set CCI-400 control override register to enable barrier
 165          * transaction
 166          */
 167         if (current_el() == 3)
 168                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 169
 170 #ifdef CONFIG_ENV_IS_NOWHERE
 171         gd->env_addr = (ulong)&default_environment[0];
 172 #endif
 173
 174 #ifdef CONFIG_FSL_CAAM
 175         sec_init();
 176 #endif
 177
 178 #ifdef CONFIG_FSL_LS_PPA
 179         ppa_init();
 180 #endif
 181         return 0;
 182 }
 183
 184 int ft_board_setup(void *blob, bd_t *bd)
 185 {
 186         arch_fixup_fdt(blob);
 187
 188         ft_cpu_setup(blob, bd);
 189
 190         return 0;
 191 }