1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/lpddr4_define.h>
11 #define WR_POST_EXT_3200 /* recommened to define */
13 static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
16 { DDRC_DBG1(0), 0x00000001 },
17 /* selfref_en=1, SDRAM enter self-refresh state */
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
25 #ifdef WR_POST_EXT_3200 /* recommened to define */
26 { DDRC_INIT4(0), 0x00330008 },
28 { DDRC_INIT4(0), 0x00310008 },
30 { DDRC_INIT6(0), 0x0066004a },
31 { DDRC_INIT7(0), 0x0006004a },
33 { DDRC_DRAMTMG0(0), 0x1A201B22 },
34 { DDRC_DRAMTMG1(0), 0x00060633 },
35 { DDRC_DRAMTMG3(0), 0x00C0C000 },
36 { DDRC_DRAMTMG4(0), 0x0F04080F },
37 { DDRC_DRAMTMG5(0), 0x02040C0C },
38 { DDRC_DRAMTMG6(0), 0x01010007 },
39 { DDRC_DRAMTMG7(0), 0x00000401 },
40 { DDRC_DRAMTMG12(0), 0x00020600 },
41 { DDRC_DRAMTMG13(0), 0x0C100002 },
42 { DDRC_DRAMTMG14(0), 0x000000E6 },
43 { DDRC_DRAMTMG17(0), 0x00A00050 },
45 { DDRC_ZQCTL0(0), 0x03200018 },
46 { DDRC_ZQCTL1(0), 0x028061A8 },
47 { DDRC_ZQCTL2(0), 0x00000000 },
49 { DDRC_DFITMG0(0), 0x0497820A },
50 { DDRC_DFITMG1(0), 0x00080303 },
51 { DDRC_DFIUPD0(0), 0xE0400018 },
52 { DDRC_DFIUPD1(0), 0x00DF00E4 },
53 { DDRC_DFIUPD2(0), 0x80000000 },
54 { DDRC_DFIMISC(0), 0x00000011 },
55 { DDRC_DFITMG2(0), 0x0000170A },
57 { DDRC_DBICTL(0), 0x00000001 },
58 { DDRC_DFIPHYMSTR(0), 0x00000001 },
60 /* need be refined by ddrphy trained value */
61 { DDRC_RANKCTL(0), 0x00000c99 },
62 { DDRC_DRAMTMG2(0), 0x070E171a },
65 /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
66 { DDRC_ADDRMAP0(0), 0x00000015 },
67 { DDRC_ADDRMAP3(0), 0x00000000 },
68 /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
69 { DDRC_ADDRMAP4(0), 0x00001F1F },
71 /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
72 { DDRC_ADDRMAP1(0), 0x00080808 },
73 /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
74 { DDRC_ADDRMAP5(0), 0x07070707 },
75 /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
76 { DDRC_ADDRMAP6(0), 0x08080707 },
78 /* 667mts frequency setting */
79 { DDRC_FREQ1_DERATEEN(0), 0x0000000 },
80 { DDRC_FREQ1_DERATEINT(0), 0x0800000 },
81 { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
82 { DDRC_FREQ1_RFSHTMG(0), 0x014001E },
83 { DDRC_FREQ1_INIT3(0), 0x0140009 },
84 { DDRC_FREQ1_INIT4(0), 0x00310008 },
85 { DDRC_FREQ1_INIT6(0), 0x0066004a },
86 { DDRC_FREQ1_INIT7(0), 0x0006004a },
87 { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
88 { DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
89 { DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
90 { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
91 { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
92 { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
93 { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
94 { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
95 { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
96 { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
97 { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
98 { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
99 { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
100 { DDRC_FREQ1_DFITMG0(0), 0x3858202 },
101 { DDRC_FREQ1_DFITMG1(0), 0x0000404 },
102 { DDRC_FREQ1_DFITMG2(0), 0x0000502 },
104 /* performance setting */
105 { DDRC_ODTCFG(0), 0x0b060908 },
106 { DDRC_ODTMAP(0), 0x00000000 },
107 { DDRC_SCHED(0), 0x29511505 },
108 { DDRC_SCHED1(0), 0x0000002c },
109 { DDRC_PERFHPR1(0), 0x5900575b },
110 /* 150T starve and 0x90 max tran len */
111 { DDRC_PERFLPR1(0), 0x90000096 },
112 /* 300T starve and 0x10 max tran len */
113 { DDRC_PERFWR1(0), 0x1000012c },
114 { DDRC_DBG0(0), 0x00000016 },
115 { DDRC_DBG1(0), 0x00000000 },
116 { DDRC_DBGCMD(0), 0x00000000 },
117 { DDRC_SWCTL(0), 0x00000001 },
118 { DDRC_POISONCFG(0), 0x00000011 },
119 { DDRC_PCCFG(0), 0x00000111 },
120 { DDRC_PCFGR_0(0), 0x000010f3 },
121 { DDRC_PCFGW_0(0), 0x000072ff },
122 { DDRC_PCTRL_0(0), 0x00000001 },
123 /* disable Read Qos*/
124 { DDRC_PCFGQOS0_0(0), 0x00000e00 },
125 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
126 /* disable Write Qos*/
127 { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
128 { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
129 { DDRC_FREQ1_DERATEEN(0), 0x00000202 },
130 { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
131 { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
132 { DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
135 /* PHY Initialize Configuration */
136 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
137 { 0x20110, 0x02 }, /* MapCAB0toDFI */
138 { 0x20111, 0x03 }, /* MapCAB1toDFI */
139 { 0x20112, 0x04 }, /* MapCAB2toDFI */
140 { 0x20113, 0x05 }, /* MapCAB3toDFI */
141 { 0x20114, 0x00 }, /* MapCAB4toDFI */
142 { 0x20115, 0x01 }, /* MapCAB5toDFI */
144 /* Initialize PHY Configuration */
320 /* P0 message block paremeter for training firmware */
321 static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
328 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
329 { 0x54006, LPDDR4_PHY_VREF_VALUE },
332 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
336 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
349 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
350 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
351 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
352 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
354 { 0x5401e, LPDDR4_MR22_RANK0 },
356 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
357 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
358 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
359 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
361 { 0x54024, LPDDR4_MR22_RANK1 },
376 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
377 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
378 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
379 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
380 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
382 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
383 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
384 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
385 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
386 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
387 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
398 /* P1 message block paremeter for training firmware */
399 static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
406 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
407 { 0x54006, LPDDR4_PHY_VREF_VALUE },
427 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
428 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
429 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
430 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
433 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
434 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
435 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
436 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
438 { 0x54024, LPDDR4_MR22_RANK1 },
453 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
454 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
455 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
456 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
459 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
460 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
461 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
462 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
463 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
474 /* P0 2D message block paremeter for training firmware */
475 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
482 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
483 { 0x54006, LPDDR4_PHY_VREF_VALUE },
486 { 0x54009, LPDDR4_HDT_CTL_2D },
490 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
492 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
493 { 0x54010, LPDDR4_2D_WEIGHT },
504 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
505 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
506 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
507 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
509 { 0x5401e, LPDDR4_MR22_RANK0 },
511 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
512 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
513 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
514 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
516 { 0x54024, LPDDR4_MR22_RANK1 },
531 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
532 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
533 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
534 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
535 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
537 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
538 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
539 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
540 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
541 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
553 /* DRAM PHY init engine image */
554 static struct dram_cfg_param lpddr4_phy_pie[] = {
1019 { 0x90186, 0x8140 },
1055 { 0x12000d, 0x1a1 },
1064 { 0x9000f, 0x6110 },
1065 { 0x90010, 0x2152 },
1066 { 0x90011, 0xdfbd },
1068 { 0x90013, 0x6152 },
1094 { 0x10002, 0x6209 },
1108 { 0x11002, 0x6209 },
1122 { 0x12002, 0x6209 },
1136 { 0x13002, 0x6209 },
1152 static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1156 .fw_type = FW_1D_IMAGE,
1157 .fsp_cfg = lpddr4_fsp0_cfg,
1158 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1163 .fw_type = FW_1D_IMAGE,
1164 .fsp_cfg = lpddr4_fsp1_cfg,
1165 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1170 .fw_type = FW_2D_IMAGE,
1171 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1172 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1176 /* lpddr4 timing config params on EVK board */
1177 struct dram_timing_info dram_timing_b0 = {
1178 .ddrc_cfg = lpddr4_ddrc_cfg,
1179 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1180 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1181 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1182 .fsp_msg = lpddr4_dram_fsp_msg,
1183 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1184 .ddrphy_pie = lpddr4_phy_pie,
1185 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1187 * this table must be initialized if DDRPHY bypass mode is
1188 * not used: all fsp drate > 666MTS.
1190 .fsp_table = { 3200, 667, },