1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/lpddr4_define.h>
11 #define WR_POST_EXT_3200 /* recommened to define */
13 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
23 #ifdef WR_POST_EXT_3200
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
28 { DDRC_INIT6(0), 0x0066004a },
29 { DDRC_INIT7(0), 0x0006004a },
31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
32 { DDRC_DRAMTMG1(0), 0x00060633 },
33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
34 { DDRC_DRAMTMG4(0), 0x0F04080F },
35 { DDRC_DRAMTMG5(0), 0x02040C0C },
36 { DDRC_DRAMTMG6(0), 0x01010007 },
37 { DDRC_DRAMTMG7(0), 0x00000401 },
38 { DDRC_DRAMTMG12(0), 0x00020600 },
39 { DDRC_DRAMTMG13(0), 0x0C100002 },
40 { DDRC_DRAMTMG14(0), 0x000000E6 },
41 { DDRC_DRAMTMG17(0), 0x00A00050 },
43 { DDRC_ZQCTL0(0), 0x03200018 },
44 { DDRC_ZQCTL1(0), 0x028061A8 },
45 { DDRC_ZQCTL2(0), 0x00000000 },
47 { DDRC_DFITMG0(0), 0x0497820A },
48 { DDRC_DFITMG1(0), 0x00080303 },
49 { DDRC_DFIUPD0(0), 0xE0400018 },
50 { DDRC_DFIUPD1(0), 0x00DF00E4 },
51 { DDRC_DFIUPD2(0), 0x80000000 },
52 { DDRC_DFIMISC(0), 0x00000011 },
53 { DDRC_DFITMG2(0), 0x0000170A },
55 { DDRC_DBICTL(0), 0x00000001 },
56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
57 { DDRC_RANKCTL(0), 0x00000c99 },
58 { DDRC_DRAMTMG2(0), 0x070E171a },
61 { DDRC_ADDRMAP0(0), 0x00000015 },
62 { DDRC_ADDRMAP3(0), 0x00000000 },
63 { DDRC_ADDRMAP4(0), 0x00001F1F },
65 { DDRC_ADDRMAP1(0), 0x00080808 },
66 { DDRC_ADDRMAP5(0), 0x07070707 },
67 { DDRC_ADDRMAP6(0), 0x08080707 },
69 /* performance setting */
70 { DDRC_ODTCFG(0), 0x0b060908 },
71 { DDRC_ODTMAP(0), 0x00000000 },
72 { DDRC_SCHED(0), 0x29511505 },
73 { DDRC_SCHED1(0), 0x0000002c },
74 { DDRC_PERFHPR1(0), 0x5900575b },
75 { DDRC_PERFLPR1(0), 0x00000009 },
76 { DDRC_PERFWR1(0), 0x02005574 },
77 { DDRC_DBG0(0), 0x00000016 },
78 { DDRC_DBG1(0), 0x00000000 },
79 { DDRC_DBGCMD(0), 0x00000000 },
80 { DDRC_SWCTL(0), 0x00000001 },
81 { DDRC_POISONCFG(0), 0x00000011 },
82 { DDRC_PCCFG(0), 0x00000111 },
83 { DDRC_PCFGR_0(0), 0x000010f3 },
84 { DDRC_PCFGW_0(0), 0x000072ff },
85 { DDRC_PCTRL_0(0), 0x00000001 },
86 { DDRC_PCFGQOS0_0(0), 0x01110d00 },
87 { DDRC_PCFGQOS1_0(0), 0x00620790 },
88 { DDRC_PCFGWQOS0_0(0), 0x00100001 },
89 { DDRC_PCFGWQOS1_0(0), 0x0000041f },
91 /* Frequency 1: 400mbps */
92 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
93 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
94 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
95 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
96 { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
97 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
98 { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
99 { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
100 { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
101 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
102 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
103 { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
104 { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
105 { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
106 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
107 { DDRC_FREQ1_INIT3(0), 0x00840000 },
108 { DDRC_FREQ1_INIT4(0), 0x00310008 },
109 { DDRC_FREQ1_INIT6(0), 0x0066004a },
110 { DDRC_FREQ1_INIT7(0), 0x0006004a },
112 /* Frequency 2: 100mbps */
113 { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
114 { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
115 { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
116 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
117 { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
118 { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
119 { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
120 { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
121 { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
122 { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
123 { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
124 { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
125 { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
126 { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
127 { DDRC_FREQ2_INIT3(0), 0x00840000 },
128 { DDRC_FREQ2_INIT4(0), 0x00310008 },
129 { DDRC_FREQ2_INIT6(0), 0x0066004a },
130 { DDRC_FREQ2_INIT7(0), 0x0006004a },
133 /* PHY Initialize Configuration */
134 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
192 #ifdef WR_POST_EXT_3200
255 { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
256 { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
257 { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
258 { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
259 { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
260 { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
261 { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
262 { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
263 { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
264 { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
327 /* P0 message block paremeter for training firmware */
328 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
335 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
336 { 0x54006, LPDDR4_PHY_VREF_VALUE },
339 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
343 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
357 #ifdef WR_POST_EXT_3200
358 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
360 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
362 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
363 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
364 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
366 { 0x5401e, LPDDR4_MR22_RANK0 },
368 #ifdef WR_POST_EXT_3200
369 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
371 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
373 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
374 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
375 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
377 { 0x54024, LPDDR4_MR22_RANK1 },
394 #ifdef WR_POST_EXT_3200
395 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
397 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
400 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
401 /* self:0x284d//MR13/MR12 */
402 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
404 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
405 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
409 #ifdef WR_POST_EXT_3200
410 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
412 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
415 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
416 /* self:0x284d//MR13/MR12 */
417 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
419 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
420 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
421 /* { 0x5403d, 0x500 } */
422 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
433 /* P1 message block paremeter for training firmware */
434 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
442 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
443 { 0x54006, LPDDR4_PHY_VREF_VALUE },
445 { 0x54008, LPDDR4_TRAIN_SEQ_400 },
446 { 0x54009, LPDDR4_HDT_CTL_400_1D },
450 { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
464 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
466 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
467 LPDDR4_RTT_DQ)/*0x4d46*/ },
468 /* self:0x4d28//MR14/MR13 */
469 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
471 { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
473 { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
474 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
475 LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
476 /* self:0x4d28//MR14/MR13 */
477 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
479 { 0x54024, LPDDR4_MR22_RANK1 },
494 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
495 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
496 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
497 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
498 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
500 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
501 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
502 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
503 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
504 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
515 /* P2 message block paremeter for training firmware */
516 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
523 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
524 { 0x54006, LPDDR4_PHY_VREF_VALUE },
526 { 0x54008, LPDDR4_TRAIN_SEQ_100 },
527 { 0x54009, LPDDR4_HDT_CTL_100_1D },
531 { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
544 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
545 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
547 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
549 { 0x5401e, LPDDR4_MR22_RANK0 },
551 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
552 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
554 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
556 { 0x54024, LPDDR4_MR22_RANK1 },
571 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
572 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
573 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
574 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
575 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
577 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
578 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
579 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
580 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
581 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
592 /* P0 2D message block paremeter for training firmware */
593 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
600 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
601 { 0x54006, LPDDR4_PHY_VREF_VALUE },
604 { 0x54009, LPDDR4_HDT_CTL_2D },
608 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
610 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
611 { 0x54010, LPDDR4_2D_WEIGHT },
621 #ifdef WR_POST_EXT_3200
622 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
624 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
626 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
627 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
628 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
630 { 0x5401e, LPDDR4_MR22_RANK0 },
632 #ifdef WR_POST_EXT_3200
633 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
635 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
637 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
638 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
639 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
641 { 0x54024, LPDDR4_MR22_RANK1 },
657 #ifdef WR_POST_EXT_3200
658 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
660 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
662 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
663 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
664 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
665 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
667 #ifdef WR_POST_EXT_3200
668 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
670 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
672 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
673 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
674 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
675 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
686 /* DRAM PHY init engine image */
687 struct dram_cfg_param lpddr4_phy_pie[] = {
1002 { 0x900f0, 0x8310 },
1005 { 0x900f3, 0xa310 },
1007 { 0x900f5, 0x1ff8 },
1008 { 0x900f6, 0x85a8 },
1020 { 0x90102, 0x8b10 },
1023 { 0x90105, 0xab10 },
1035 { 0x90111, 0x8b10 },
1038 { 0x90114, 0xab10 },
1053 { 0x90123, 0x8080 },
1068 { 0x90132, 0x8080 },
1074 { 0x90138, 0x8568 },
1083 { 0x90141, 0x8558 },
1095 { 0x9014d, 0x8558 },
1113 { 0x9015f, 0x8140 },
1116 { 0x90162, 0x8138 },
1146 { 0x90180, 0x8140 },
1191 { 0x9000f, 0x6110 },
1192 { 0x90010, 0x2152 },
1193 { 0x90011, 0xdfbd },
1195 { 0x90013, 0x6152 },
1221 { 0x10002, 0x6209 },
1235 { 0x11002, 0x6209 },
1249 { 0x12002, 0x6209 },
1263 { 0x13002, 0x6209 },
1278 struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1282 .fw_type = FW_1D_IMAGE,
1283 .fsp_cfg = lpddr4_fsp0_cfg,
1284 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1289 .fw_type = FW_1D_IMAGE,
1290 .fsp_cfg = lpddr4_fsp1_cfg,
1291 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1296 .fw_type = FW_1D_IMAGE,
1297 .fsp_cfg = lpddr4_fsp2_cfg,
1298 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1303 .fw_type = FW_2D_IMAGE,
1304 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1305 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1309 /* lpddr4 timing config params on EVK board */
1310 struct dram_timing_info dram_timing = {
1311 .ddrc_cfg = lpddr4_ddrc_cfg,
1312 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1313 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1314 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1315 .fsp_msg = lpddr4_dram_fsp_msg,
1316 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1317 .ddrphy_pie = lpddr4_phy_pie,
1318 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1319 .fsp_table = { 3200, 400, 100, },