1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/lpddr4_define.h>
11 #define WR_POST_EXT_3200 /* recommened to define */
13 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
14 /* Start to config, default 3200mbps */
15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
23 #ifdef WR_POST_EXT_3200
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
28 { DDRC_INIT6(0), 0x0066004a },
29 { DDRC_INIT7(0), 0x0006004a },
31 { DDRC_DRAMTMG0(0), 0x1A201B22 },
32 { DDRC_DRAMTMG1(0), 0x00060633 },
33 { DDRC_DRAMTMG3(0), 0x00C0C000 },
34 { DDRC_DRAMTMG4(0), 0x0F04080F },
35 { DDRC_DRAMTMG5(0), 0x02040C0C },
36 { DDRC_DRAMTMG6(0), 0x01010007 },
37 { DDRC_DRAMTMG7(0), 0x00000401 },
38 { DDRC_DRAMTMG12(0), 0x00020600 },
39 { DDRC_DRAMTMG13(0), 0x0C100002 },
40 { DDRC_DRAMTMG14(0), 0x000000E6 },
41 { DDRC_DRAMTMG17(0), 0x00A00050 },
43 { DDRC_ZQCTL0(0), 0x03200018 },
44 { DDRC_ZQCTL1(0), 0x028061A8 },
45 { DDRC_ZQCTL2(0), 0x00000000 },
47 { DDRC_DFITMG0(0), 0x0497820A },
48 { DDRC_DFITMG1(0), 0x00080303 },
49 { DDRC_DFIUPD0(0), 0xE0400018 },
50 { DDRC_DFIUPD1(0), 0x00DF00E4 },
51 { DDRC_DFIUPD2(0), 0x80000000 },
52 { DDRC_DFIMISC(0), 0x00000011 },
53 { DDRC_DFITMG2(0), 0x0000170A },
55 { DDRC_DBICTL(0), 0x00000001 },
56 { DDRC_DFIPHYMSTR(0), 0x00000001 },
57 { DDRC_RANKCTL(0), 0x00000c99 },
58 { DDRC_DRAMTMG2(0), 0x070E171a },
61 { DDRC_ADDRMAP0(0), 0x00000015 },
62 { DDRC_ADDRMAP3(0), 0x00000000 },
63 { DDRC_ADDRMAP4(0), 0x00001F1F },
65 { DDRC_ADDRMAP1(0), 0x00080808 },
66 { DDRC_ADDRMAP5(0), 0x07070707 },
67 { DDRC_ADDRMAP6(0), 0x08080707 },
69 /* performance setting */
70 { DDRC_ODTCFG(0), 0x0b060908 },
71 { DDRC_ODTMAP(0), 0x00000000 },
72 { DDRC_SCHED(0), 0x29511505 },
73 { DDRC_SCHED1(0), 0x0000002c },
74 { DDRC_PERFHPR1(0), 0x5900575b },
75 /* 150T starve and 0x90 max tran len */
76 { DDRC_PERFLPR1(0), 0x90000096 },
77 /* 300T starve and 0x10 max tran len */
78 { DDRC_PERFWR1(0), 0x1000012c },
79 { DDRC_DBG0(0), 0x00000016 },
80 { DDRC_DBG1(0), 0x00000000 },
81 { DDRC_DBGCMD(0), 0x00000000 },
82 { DDRC_SWCTL(0), 0x00000001 },
83 { DDRC_POISONCFG(0), 0x00000011 },
84 { DDRC_PCCFG(0), 0x00000111 },
85 { DDRC_PCFGR_0(0), 0x000010f3 },
86 { DDRC_PCFGW_0(0), 0x000072ff },
87 { DDRC_PCTRL_0(0), 0x00000001 },
89 { DDRC_PCFGQOS0_0(0), 0x00000e00 },
90 { DDRC_PCFGQOS1_0(0), 0x0062ffff },
91 /* disable Write Qos*/
92 { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
93 { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
95 /* Frequency 1: 400mbps */
96 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
97 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
98 { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
99 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
100 { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
101 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
102 { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
103 { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
104 { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
105 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
106 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
107 { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
108 { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
109 { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
110 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
111 { DDRC_FREQ1_INIT3(0), 0x00840000 },
112 { DDRC_FREQ1_INIT4(0), 0x00310008 },
113 { DDRC_FREQ1_INIT6(0), 0x0066004a },
114 { DDRC_FREQ1_INIT7(0), 0x0006004a },
116 /* Frequency 2: 100mbps */
117 { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
118 { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
119 { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
120 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
121 { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
122 { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
123 { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
124 { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
125 { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
126 { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
127 { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
128 { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
129 { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
130 { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
131 { DDRC_FREQ2_INIT3(0), 0x00840000 },
132 { DDRC_FREQ2_INIT4(0), 0x00310008 },
133 { DDRC_FREQ2_INIT6(0), 0x0066004a },
134 { DDRC_FREQ2_INIT7(0), 0x0006004a },
137 /* PHY Initialize Configuration */
138 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
196 #ifdef WR_POST_EXT_3200
259 { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
260 { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
261 { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
262 { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
263 { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
264 { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
265 { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
266 { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
267 { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
268 { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
331 /* P0 message block paremeter for training firmware */
332 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
339 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
340 { 0x54006, LPDDR4_PHY_VREF_VALUE },
343 { 0x54009, LPDDR4_HDT_CTL_3200_1D },
347 { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
361 #ifdef WR_POST_EXT_3200
362 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
364 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
366 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
367 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
368 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
370 { 0x5401e, LPDDR4_MR22_RANK0 },
372 #ifdef WR_POST_EXT_3200
373 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
375 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
377 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
378 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
379 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
381 { 0x54024, LPDDR4_MR22_RANK1 },
398 #ifdef WR_POST_EXT_3200
399 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
401 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
404 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
405 /* self:0x284d//MR13/MR12 */
406 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
408 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
409 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
413 #ifdef WR_POST_EXT_3200
414 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
416 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
419 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
420 /* self:0x284d//MR13/MR12 */
421 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
423 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
424 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
425 /* { 0x5403d, 0x500 } */
426 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
437 /* P1 message block paremeter for training firmware */
438 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
446 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
447 { 0x54006, LPDDR4_PHY_VREF_VALUE },
449 { 0x54008, LPDDR4_TRAIN_SEQ_400 },
450 { 0x54009, LPDDR4_HDT_CTL_400_1D },
454 { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
468 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
470 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
471 LPDDR4_RTT_DQ)/*0x4d46*/ },
472 /* self:0x4d28//MR14/MR13 */
473 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
475 { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
477 { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
478 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
479 LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
480 /* self:0x4d28//MR14/MR13 */
481 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
483 { 0x54024, LPDDR4_MR22_RANK1 },
498 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
499 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
500 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
501 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
502 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
504 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
505 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
506 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
507 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
508 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
519 /* P2 message block paremeter for training firmware */
520 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
527 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
528 { 0x54006, LPDDR4_PHY_VREF_VALUE },
530 { 0x54008, LPDDR4_TRAIN_SEQ_100 },
531 { 0x54009, LPDDR4_HDT_CTL_100_1D },
535 { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
548 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
549 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
551 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
553 { 0x5401e, LPDDR4_MR22_RANK0 },
555 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
556 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
558 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
560 { 0x54024, LPDDR4_MR22_RANK1 },
575 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
576 { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
577 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
578 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
579 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
581 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
582 { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
583 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
584 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
585 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
596 /* P0 2D message block paremeter for training firmware */
597 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
604 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
605 { 0x54006, LPDDR4_PHY_VREF_VALUE },
608 { 0x54009, LPDDR4_HDT_CTL_2D },
612 { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
614 { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
615 { 0x54010, LPDDR4_2D_WEIGHT },
625 #ifdef WR_POST_EXT_3200
626 { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
628 { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
630 { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
631 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
632 { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
634 { 0x5401e, LPDDR4_MR22_RANK0 },
636 #ifdef WR_POST_EXT_3200
637 { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
639 { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
641 { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
642 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
643 { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
645 { 0x54024, LPDDR4_MR22_RANK1 },
661 #ifdef WR_POST_EXT_3200
662 { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
664 { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
666 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
667 { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
668 { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
669 { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
671 #ifdef WR_POST_EXT_3200
672 { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
674 { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
676 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
677 { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
678 { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
679 { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
690 /* DRAM PHY init engine image */
691 struct dram_cfg_param lpddr4_phy_pie[] = {
1006 { 0x900f0, 0x8310 },
1009 { 0x900f3, 0xa310 },
1011 { 0x900f5, 0x1ff8 },
1012 { 0x900f6, 0x85a8 },
1024 { 0x90102, 0x8b10 },
1027 { 0x90105, 0xab10 },
1039 { 0x90111, 0x8b10 },
1042 { 0x90114, 0xab10 },
1057 { 0x90123, 0x8080 },
1072 { 0x90132, 0x8080 },
1078 { 0x90138, 0x8568 },
1087 { 0x90141, 0x8558 },
1099 { 0x9014d, 0x8558 },
1117 { 0x9015f, 0x8140 },
1120 { 0x90162, 0x8138 },
1150 { 0x90180, 0x8140 },
1195 { 0x9000f, 0x6110 },
1196 { 0x90010, 0x2152 },
1197 { 0x90011, 0xdfbd },
1199 { 0x90013, 0x6152 },
1225 { 0x10002, 0x6209 },
1239 { 0x11002, 0x6209 },
1253 { 0x12002, 0x6209 },
1267 { 0x13002, 0x6209 },
1282 struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1286 .fw_type = FW_1D_IMAGE,
1287 .fsp_cfg = lpddr4_fsp0_cfg,
1288 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1293 .fw_type = FW_1D_IMAGE,
1294 .fsp_cfg = lpddr4_fsp1_cfg,
1295 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1300 .fw_type = FW_1D_IMAGE,
1301 .fsp_cfg = lpddr4_fsp2_cfg,
1302 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1307 .fw_type = FW_2D_IMAGE,
1308 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1309 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1313 /* lpddr4 timing config params on EVK board */
1314 struct dram_timing_info dram_timing = {
1315 .ddrc_cfg = lpddr4_ddrc_cfg,
1316 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1317 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1318 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1319 .fsp_msg = lpddr4_dram_fsp_msg,
1320 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1321 .ddrphy_pie = lpddr4_phy_pie,
1322 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
1323 .fsp_table = { 3200, 400, 100, },