board/freescale/imx8mp_evk/spl.c

   1 /*
   2  * Copyright 2018-2019 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <spl.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <asm/io.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/arch/imx8mp_pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <power/pmic.h>
  17
  18 #include <power/pca9450.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/mach-imx/gpio.h>
  21 #include <asm/mach-imx/mxc_i2c.h>
  22 #include <fsl_esdhc.h>
  23 #include <mmc.h>
  24 #include <asm/arch/ddr.h>
  25
  26 #include <dm/uclass.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass-internal.h>
  29 #include <dm/device-internal.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int spl_board_boot_device(enum boot_device boot_dev_spl)
  34 {
  35         return BOOT_DEVICE_BOOTROM;
  36 }
  37
  38 void spl_dram_init(void)
  39 {
  40         ddr_init(&dram_timing);
  41 }
  42
  43 void spl_board_init(void)
  44 {
  45         struct udevice *dev;
  46         int ret;
  47
  48         puts("Normal Boot\n");
  49
  50         ret = uclass_get_device_by_name(UCLASS_CLK,
  51                                         "clock-controller@30380000",
  52                                         &dev);
  53         if (ret < 0)
  54                 printf("Failed to find clock node. Check device tree\n");
  55 }
  56
  57 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  58 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  59 struct i2c_pads_info i2c_pad_info1 = {
  60         .scl = {
  61                 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  62                 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  63                 .gp = IMX_GPIO_NR(5, 14),
  64         },
  65         .sda = {
  66                 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  67                 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  68                 .gp = IMX_GPIO_NR(5, 15),
  69         },
  70 };
  71
  72 #ifdef CONFIG_POWER
  73 #define I2C_PMIC        0
  74 int power_init_board(void)
  75 {
  76         struct pmic *p;
  77         int ret;
  78
  79         ret = power_pca9450b_init(I2C_PMIC);
  80         if (ret)
  81                 printf("power init failed");
  82         p = pmic_get("PCA9450");
  83         pmic_probe(p);
  84
  85         /* BUCKxOUT_DVS0/1 control BUCK123 output */
  86         pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  87
  88         /*
  89          * increase VDD_SOC to typical value 0.95V before first
  90          * DRAM access, set DVS1 to 0.85v for suspend.
  91          * Enable DVS control through PMIC_STBY_REQ and
  92          * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  93          */
  94         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  95         pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  96         pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  97
  98         /* set WDOG_B_CFG to cold reset */
  99         pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
 100
 101         return 0;
 102 }
 103 #endif
 104
 105 #ifdef CONFIG_SPL_LOAD_FIT
 106 int board_fit_config_name_match(const char *name)
 107 {
 108         /* Just empty function now - can't decide what to choose */
 109         debug("%s: %s\n", __func__, name);
 110
 111         return 0;
 112 }
 113 #endif
 114
 115 void board_init_f(ulong dummy)
 116 {
 117         int ret;
 118
 119         arch_cpu_init();
 120
 121         init_uart_clk(1);
 122
 123         board_early_init_f();
 124
 125         timer_init();
 126
 127         preloader_console_init();
 128
 129         /* Clear the BSS. */
 130         memset(__bss_start, 0, __bss_end - __bss_start);
 131
 132         ret = spl_init();
 133         if (ret) {
 134                 debug("spl_init() failed: %d\n", ret);
 135                 hang();
 136         }
 137
 138         enable_tzc380();
 139
 140         /* Adjust pmic voltage to 1.0V for 800M */
 141         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 142
 143         power_init_board();
 144
 145         /* DDR initialization */
 146         spl_dram_init();
 147
 148         board_init_r(NULL, 0);
 149 }
 150
 151 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 152 {
 153         puts("resetting ...\n");
 154
 155         reset_cpu(WDOG1_BASE_ADDR);
 156
 157         return 0;
 158 }