board/freescale/imx8mm_evk/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <image.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <spl.h>
  14 #include <asm/io.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/imx8mm_pins.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/arch/ddr.h>
  21
  22 #include <dm/uclass.h>
  23 #include <dm/device.h>
  24 #include <dm/uclass-internal.h>
  25 #include <dm/device-internal.h>
  26
  27 #include <power/pmic.h>
  28 #include <power/bd71837.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 int spl_board_boot_device(enum boot_device boot_dev_spl)
  33 {
  34         switch (boot_dev_spl) {
  35         case SD2_BOOT:
  36         case MMC2_BOOT:
  37                 return BOOT_DEVICE_MMC1;
  38         case SD3_BOOT:
  39         case MMC3_BOOT:
  40                 return BOOT_DEVICE_MMC2;
  41         default:
  42                 return BOOT_DEVICE_NONE;
  43         }
  44 }
  45
  46 static void spl_dram_init(void)
  47 {
  48         ddr_init(&dram_timing);
  49 }
  50
  51 void spl_board_init(void)
  52 {
  53         puts("Normal Boot\n");
  54 }
  55
  56 #ifdef CONFIG_SPL_LOAD_FIT
  57 int board_fit_config_name_match(const char *name)
  58 {
  59         /* Just empty function now - can't decide what to choose */
  60         debug("%s: %s\n", __func__, name);
  61
  62         return 0;
  63 }
  64 #endif
  65
  66 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  67 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  68
  69 static iomux_v3_cfg_t const uart_pads[] = {
  70         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  71         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  72 };
  73
  74 static iomux_v3_cfg_t const wdog_pads[] = {
  75         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  76 };
  77
  78 int board_early_init_f(void)
  79 {
  80         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  81
  82         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  83
  84         set_wdog_reset(wdog);
  85
  86         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  87
  88         return 0;
  89 }
  90
  91 static int power_init_board(void)
  92 {
  93         struct udevice *dev;
  94         int ret;
  95
  96         ret = pmic_get("pmic@4b", &dev);
  97         if (ret == -ENODEV) {
  98                 puts("No pmic\n");
  99                 return 0;
 100         }
 101         if (ret != 0)
 102                 return ret;
 103
 104         /* decrease RESET key long push time from the default 10s to 10ms */
 105         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 106
 107         /* unlock the PMIC regs */
 108         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 109
 110         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 111         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 112
 113         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 114         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 115
 116 #ifndef CONFIG_IMX8M_LPDDR4
 117         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 118         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 119 #endif
 120
 121         /* lock the PMIC regs */
 122         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 123
 124         return 0;
 125 }
 126
 127 void board_init_f(ulong dummy)
 128 {
 129         struct udevice *dev;
 130         int ret;
 131
 132         arch_cpu_init();
 133
 134         init_uart_clk(1);
 135
 136         board_early_init_f();
 137
 138         timer_init();
 139
 140         preloader_console_init();
 141
 142         /* Clear the BSS. */
 143         memset(__bss_start, 0, __bss_end - __bss_start);
 144
 145         ret = spl_early_init();
 146         if (ret) {
 147                 debug("spl_early_init() failed: %d\n", ret);
 148                 hang();
 149         }
 150
 151         ret = uclass_get_device_by_name(UCLASS_CLK,
 152                                         "clock-controller@30380000",
 153                                         &dev);
 154         if (ret < 0) {
 155                 printf("Failed to find clock node. Check device tree\n");
 156                 hang();
 157         }
 158
 159         enable_tzc380();
 160
 161         power_init_board();
 162
 163         /* DDR initialization */
 164         spl_dram_init();
 165
 166         board_init_r(NULL, 0);
 167 }