2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
32 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
33 MAS3_SX|MAS3_SW|MAS3_SR, 0,
34 0, 0, BOOKE_PAGESZ_4K, 0),
35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
36 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
37 MAS3_SX|MAS3_SW|MAS3_SR, 0,
38 0, 0, BOOKE_PAGESZ_4K, 0),
39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
40 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
44 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
45 MAS3_SX|MAS3_SW|MAS3_SR, 0,
46 0, 0, BOOKE_PAGESZ_4K, 0),
48 SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
50 0, 0, BOOKE_PAGESZ_4K, 0),
53 /* *I*** - Covers boot page */
54 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56 0, 0, BOOKE_PAGESZ_4K, 1),
59 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
60 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
61 0, 1, BOOKE_PAGESZ_16M, 1),
63 /* *I*G* - Flash, localbus */
64 /* This will be changed to *I*G* after relocation to RAM. */
65 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
66 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
72 0, 3, BOOKE_PAGESZ_1G, 1),
75 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
76 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
78 0, 4, BOOKE_PAGESZ_256M, 1),
80 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
81 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, 5, BOOKE_PAGESZ_256M, 1),
86 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88 0, 6, BOOKE_PAGESZ_256K, 1),
91 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
92 MAS3_SX|MAS3_SW|MAS3_SR, 0,
93 0, 9, BOOKE_PAGESZ_1M, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
95 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
96 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
97 0, 10, BOOKE_PAGESZ_1M, 1),
98 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
99 MAS3_SX|MAS3_SW|MAS3_SR, 0,
100 0, 11, BOOKE_PAGESZ_1M, 1),
101 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
102 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
103 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
104 0, 12, BOOKE_PAGESZ_1M, 1),
105 #ifdef CONFIG_SYS_DCSRBAR_PHYS
106 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
107 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
108 0, 13, BOOKE_PAGESZ_4M, 1),
112 int num_tlb_entries = ARRAY_SIZE(tlb_table);