2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/fsl_pci.h>
28 #include <fdt_support.h>
29 #include <asm/fsl_serdes.h>
32 static struct pci_controller pcie1_hose;
36 static struct pci_controller pcie2_hose;
40 static struct pci_controller pcie3_hose;
44 static struct pci_controller pcie4_hose;
47 void pci_init_board(void)
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 struct fsl_pci_info pci_info[4];
52 int first_free_busno = 0;
55 int pcie_ep, pcie_configured;
57 devdisr = in_be32(&gur->devdisr);
59 debug (" pci_init_board: devdisr=%x\n", devdisr);
62 pcie_configured = is_serdes_configured(PCIE1);
64 if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
65 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
67 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
69 SET_STD_PCIE_INFO(pci_info[num], 1);
70 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
71 printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
72 pcie_ep ? "End Point" : "Root Complex",
74 first_free_busno = fsl_pci_init_port(&pci_info[num++],
75 &pcie1_hose, first_free_busno);
77 printf("PCIE1: disabled\n");
80 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
84 pcie_configured = is_serdes_configured(PCIE2);
86 if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
87 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
89 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
91 SET_STD_PCIE_INFO(pci_info[num], 2);
92 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
93 printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
94 pcie_ep ? "End Point" : "Root Complex",
96 first_free_busno = fsl_pci_init_port(&pci_info[num++],
97 &pcie2_hose, first_free_busno);
99 printf("PCIE2: disabled\n");
102 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
106 pcie_configured = is_serdes_configured(PCIE3);
108 if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
109 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
111 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
113 SET_STD_PCIE_INFO(pci_info[num], 3);
114 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
115 printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
116 pcie_ep ? "End Point" : "Root Complex",
118 first_free_busno = fsl_pci_init_port(&pci_info[num++],
119 &pcie3_hose, first_free_busno);
121 printf("PCIE3: disabled\n");
124 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
128 pcie_configured = is_serdes_configured(PCIE4);
130 if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
131 set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
133 set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
135 SET_STD_PCIE_INFO(pci_info[num], 4);
136 pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
137 printf("PCIE4: connected to as %s (base addr %lx)\n",
138 pcie_ep ? "End Point" : "Root Complex",
140 first_free_busno = fsl_pci_init_port(&pci_info[num++],
141 &pcie4_hose, first_free_busno);
143 printf("PCIE4: disabled\n");
146 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
150 void pci_of_setup(void *blob, bd_t *bd)