2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
20 unsigned int ctrl_num);
24 * Fixed sdram init -- doesn't use serial presence detect.
26 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
27 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
28 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
31 phys_size_t fixed_sdram(void)
36 fsl_ddr_cfg_regs_t ddr_cfg_regs;
38 unsigned int lawbar1_target_id;
40 get_sys_info(&sysinfo);
41 printf("Configuring DDR for %s MT/s data rate\n",
42 strmhz(buf, sysinfo.freqDDRBus));
44 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
45 if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
46 (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
48 fixed_ddr_parm_0[i].ddr_settings,
49 sizeof(ddr_cfg_regs));
54 if (fixed_ddr_parm_0[i].max_freq == 0)
55 panic("Unsupported DDR data rate %s MT/s data rate\n",
56 strmhz(buf, sysinfo.freqDDRBus));
58 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
60 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
62 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
64 fixed_ddr_parm_1[i].ddr_settings,
65 sizeof(ddr_cfg_regs));
66 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
67 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
71 * setup laws for DDR. If not interleaving, presuming half memory on
72 * DDR1 and the other half on DDR2
74 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
75 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
77 LAW_TRGT_IF_DDR_INTRLV) < 0) {
78 printf("ERROR setting Local Access Windows for DDR\n");
82 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
83 /* We require both controllers have identical DIMMs */
84 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
85 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
87 lawbar1_target_id) < 0) {
88 printf("ERROR setting Local Access Windows for DDR\n");
91 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
92 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
94 lawbar1_target_id) < 0) {
95 printf("ERROR setting Local Access Windows for DDR\n");
99 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
100 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
102 lawbar1_target_id) < 0) {
103 printf("ERROR setting Local Access Windows for DDR\n");
111 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
115 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
117 debug("DDR: failed to read SPD from address %u\n", i2c_address);
118 memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
122 unsigned int fsl_ddr_get_mem_data_rate(void)
124 return get_ddr_freq(0);
127 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
128 unsigned int ctrl_num)
131 unsigned int i2c_address = 0;
133 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
134 if (ctrl_num == 0 && i == 0)
135 i2c_address = SPD_EEPROM_ADDRESS1;
136 else if (ctrl_num == 1 && i == 0)
137 i2c_address = SPD_EEPROM_ADDRESS2;
139 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
144 u32 datarate_mhz_low;
145 u32 datarate_mhz_high;
150 u32 write_data_delay;
152 } board_specific_parameters_t;
154 /* ranges for parameters:
155 * wr_data_delay = 0-6
161 /* XXX: these values need to be checked for all interleaving modes. */
162 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may
163 * seem reliable, but errors will appear when memory intensive
165 /* XXX: Single rank at 800 MHz is OK. */
166 const board_specific_parameters_t board_specific_parameters[][30] = {
169 * memory controller 0
170 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
171 * mhz| mhz|ranks|adjst| start | delay|
173 { 0, 850, 4, 1, 5, 0xff, 2, 0},
174 {851, 950, 4, 3, 5, 0xff, 2, 0},
175 {951, 1050, 4, 5, 8, 0xff, 2, 0},
176 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
177 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
178 { 0, 850, 2, 5, 6, 0xff, 2, 0},
179 {851, 950, 2, 5, 7, 0xff, 2, 0},
180 {951, 1050, 2, 5, 7, 0xff, 2, 0},
181 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
182 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
187 * memory controller 1
188 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
189 * mhz| mhz|ranks|adjst| start | delay|
191 { 0, 850, 4, 1, 5, 0xff, 2, 0},
192 {851, 950, 4, 3, 5, 0xff, 2, 0},
193 {951, 1050, 4, 5, 8, 0xff, 2, 0},
194 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
195 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
196 { 0, 850, 2, 5, 6, 0xff, 2, 0},
197 {851, 950, 2, 5, 7, 0xff, 2, 0},
198 {951, 1050, 2, 5, 7, 0xff, 2, 0},
199 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
200 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
204 void fsl_ddr_board_options(memctl_options_t *popts,
205 dimm_params_t *pdimm,
206 unsigned int ctrl_num)
208 const board_specific_parameters_t *pbsp =
209 &(board_specific_parameters[ctrl_num][0]);
210 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
211 sizeof(board_specific_parameters[0][0]);
215 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
216 * freqency and n_banks specified in board_specific_parameters table.
218 ddr_freq = get_ddr_freq(0) / 1000000;
219 for (i = 0; i < num_params; i++) {
220 if (ddr_freq >= pbsp->datarate_mhz_low &&
221 ddr_freq <= pbsp->datarate_mhz_high &&
222 pdimm[0].n_ranks == pbsp->n_ranks) {
223 popts->cpo_override = pbsp->cpo;
224 popts->write_data_delay = pbsp->write_data_delay;
225 popts->clk_adjust = pbsp->clk_adjust;
226 popts->wrlvl_start = pbsp->wrlvl_start;
227 popts->twoT_en = pbsp->force_2T;
233 * Factors to consider for half-strength driver enable:
234 * - number of DIMMs installed
236 popts->half_strength_driver_enable = 0;
238 * Write leveling override
240 popts->wrlvl_override = 1;
241 popts->wrlvl_sample = 0xf;
244 * Rtt and Rtt_WR override
246 popts->rtt_override = 0;
248 /* Enable ZQ calibration */
251 /* DHC_EN =1, ODT = 60 Ohm */
252 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
254 /* override SPD values. rcw_2 should vary at differnt speed */
255 if (pdimm[0].n_ranks == 4) {
256 popts->rcw_override = 1;
257 popts->rcw_1 = 0x000a5a00;
259 popts->rcw_2 = 0x00000000;
260 else if (ddr_freq <= 1066)
261 popts->rcw_2 = 0x00100000;
262 else if (ddr_freq <= 1333)
263 popts->rcw_2 = 0x00200000;
265 popts->rcw_2 = 0x00300000;
269 phys_size_t initdram(int board_type)
271 phys_size_t dram_size;
273 puts("Initializing....");
277 dram_size = fsl_ddr_sdram();
279 puts("using fixed parameters\n");
280 dram_size = fixed_sdram();
283 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
284 dram_size *= 0x100000;