2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
12 #include <asm/fsl_ddr_sdram.h>
13 #include <asm/fsl_ddr_dimm_params.h>
15 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
19 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
21 debug("DDR: failed to read SPD from address %u\n", i2c_address);
22 memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
26 unsigned int fsl_ddr_get_mem_data_rate(void)
28 return get_ddr_freq(0);
31 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
32 unsigned int ctrl_num)
35 unsigned int i2c_address = 0;
37 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
38 if (ctrl_num == 0 && i == 0)
39 i2c_address = SPD_EEPROM_ADDRESS1;
40 else if (ctrl_num == 1 && i == 0)
41 i2c_address = SPD_EEPROM_ADDRESS2;
43 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
49 u32 datarate_mhz_high;
55 } board_specific_parameters_t;
57 /* ranges for parameters:
64 /* XXX: these values need to be checked for all interleaving modes. */
65 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may
66 * seem reliable, but errors will appear when memory intensive
68 /* XXX: Single rank at 800 MHz is OK. */
69 const board_specific_parameters_t board_specific_parameters[][20] = {
71 /* memory controller 0 */
72 /* lo| hi| num| clk| cpo|wrdata|2T */
73 /* mhz| mhz|ranks|adjst| | delay| */
74 { 0, 333, 2, 6, 7, 3, 0},
75 {334, 400, 2, 6, 9, 3, 0},
76 {401, 549, 2, 6, 11, 3, 0},
77 {550, 680, 2, 1, 10, 5, 0},
78 {681, 850, 2, 1, 12, 5, 0},
79 {851, 1050, 2, 1, 12, 5, 0},
80 {1051, 1250, 2, 1, 15, 4, 0},
81 {1251, 1350, 2, 1, 15, 4, 0},
82 { 0, 333, 1, 6, 7, 3, 0},
83 {334, 400, 1, 6, 9, 3, 0},
84 {401, 549, 1, 6, 11, 3, 0},
85 {550, 680, 1, 1, 10, 5, 0},
86 {681, 850, 1, 1, 12, 5, 0}
90 /* memory controller 1 */
91 /* lo| hi| num| clk| cpo|wrdata|2T */
92 /* mhz| mhz|ranks|adjst| | delay| */
93 { 0, 333, 2, 6, 7, 3, 0},
94 {334, 400, 2, 6, 9, 3, 0},
95 {401, 549, 2, 6, 11, 3, 0},
96 {550, 680, 2, 1, 11, 6, 0},
97 {681, 850, 2, 1, 13, 6, 0},
98 {851, 1050, 2, 1, 13, 6, 0},
99 {1051, 1250, 2, 1, 15, 4, 0},
100 {1251, 1350, 2, 1, 15, 4, 0},
101 { 0, 333, 1, 6, 7, 3, 0},
102 {334, 400, 1, 6, 9, 3, 0},
103 {401, 549, 1, 6, 11, 3, 0},
104 {550, 680, 1, 1, 11, 6, 0},
105 {681, 850, 1, 1, 13, 6, 0}
109 void fsl_ddr_board_options(memctl_options_t *popts,
110 dimm_params_t *pdimm,
111 unsigned int ctrl_num)
113 const board_specific_parameters_t *pbsp =
114 &(board_specific_parameters[ctrl_num][0]);
115 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
116 sizeof(board_specific_parameters[0][0]);
120 /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
121 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
122 * there are two dimms in the controller, set odt_rd_cfg to 3 and
123 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
125 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
126 if (i&1) { /* odd CS */
127 popts->cs_local_opts[i].odt_rd_cfg = 0;
128 popts->cs_local_opts[i].odt_wr_cfg = 1;
129 } else { /* even CS */
130 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
131 popts->cs_local_opts[i].odt_rd_cfg = 0;
132 popts->cs_local_opts[i].odt_wr_cfg = 1;
133 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
134 popts->cs_local_opts[i].odt_rd_cfg = 3;
135 popts->cs_local_opts[i].odt_wr_cfg = 3;
140 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
141 * freqency and n_banks specified in board_specific_parameters table.
143 ddr_freq = get_ddr_freq(0) / 1000000;
144 for (i = 0; i < num_params; i++) {
145 if (ddr_freq >= pbsp->datarate_mhz_low &&
146 ddr_freq <= pbsp->datarate_mhz_high &&
147 pdimm->n_ranks == pbsp->n_ranks) {
148 popts->cpo_override = 0xff; /* force auto CPO calibration */
149 popts->write_data_delay = 2;
150 popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
151 popts->twoT_en = pbsp->force_2T;
157 * Factors to consider for half-strength driver enable:
158 * - number of DIMMs installed
160 popts->half_strength_driver_enable = 0;
162 * Write leveling override
164 popts->wrlvl_override = 1;
165 popts->wrlvl_sample = 0xa;
166 popts->wrlvl_start = 0x7;
168 * Rtt and Rtt_WR override
170 popts->rtt_override = 1;
171 popts->rtt_override_value = DDR3_RTT_120_OHM;
172 popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
174 /* Enable ZQ calibration */