2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
36 extern void pci_of_setup(void *blob, bd_t *bd);
38 #include "../common/ngpixis.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 void cpu_mp_lmb_reserve(struct lmb *lmb);
47 struct cpu_type *cpu = gd->cpu;
49 printf("Board: %sDS, ", cpu->name);
50 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
51 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
53 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
54 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
57 printf("vBank: %d\n", sw);
63 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
65 #ifdef CONFIG_PHYS_64BIT
66 puts("36-bit Addressing\n");
69 /* Display the actual SERDES reference clocks as configured by the
70 * dip switches on the board. Note that the SWx registers could
71 * technically be set to force the reference clocks to match the
72 * values that the SERDES expects (or vice versa). For now, however,
73 * we just display both values and hope the user notices when they
76 puts("SERDES Reference Clocks: ");
77 sw = in_8(&PIXIS_SW(3));
78 printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
79 printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
80 printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
85 int board_early_init_f(void)
87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
91 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
92 * the noise introduced by these unterminated and unused clock pairs.
94 setbits_be32(&gur->ddrclkdr, 0x001B001B);
99 int board_early_init_r(void)
101 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
102 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
105 * Remap Boot flash + PROMJET region to caching-inhibited
106 * so that flash can be erased properly.
109 /* Flush d-cache and invalidate i-cache of any FLASH data */
113 /* invalidate existing TLB entry for flash + promjet */
114 disable_tlb(flash_esel);
116 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
117 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
118 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
124 if (is_serdes_configured(SRIO1)) {
125 set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
128 printf (" SRIO1: disabled\n");
131 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
135 if (is_serdes_configured(SRIO2)) {
136 set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
139 printf (" SRIO2: disabled\n");
142 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
148 static const char *serdes_clock_to_string(u32 clock)
151 case SRDS_PLLCR0_RFCK_SEL_100:
153 case SRDS_PLLCR0_RFCK_SEL_125:
155 case SRDS_PLLCR0_RFCK_SEL_156_25:
162 #define NUM_SRDS_BANKS 3
164 int misc_init_r(void)
166 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
167 u32 actual[NUM_SRDS_BANKS];
171 /* Warn if the expected SERDES reference clocks don't match the
172 * actual reference clocks. This needs to be done after calling
173 * p4080_erratum_serdes8(), since that function may modify the clocks.
175 sw3 = in_8(&PIXIS_SW(3));
176 actual[0] = (sw3 & 0x40) ?
177 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
178 actual[1] = (sw3 & 0x20) ?
179 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
180 actual[2] = (sw3 & 0x10) ?
181 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
183 for (i = 0; i < NUM_SRDS_BANKS; i++) {
184 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
185 if (expected != actual[i]) {
186 printf("Warning: SERDES bank %u expects reference clock"
187 " %sMHz, but actual is %sMHz\n", i + 1,
188 serdes_clock_to_string(expected),
189 serdes_clock_to_string(actual[i]));
196 phys_size_t initdram(int board_type)
198 phys_size_t dram_size;
200 puts("Initializing....\n");
202 dram_size = fsl_ddr_sdram();
204 setup_ddr_tlbs(dram_size / 0x100000);
211 void board_lmb_reserve(struct lmb *lmb)
213 cpu_mp_lmb_reserve(lmb);
217 void ft_srio_setup(void *blob)
220 if (!is_serdes_configured(SRIO1)) {
221 fdt_del_node_and_alias(blob, "rio0");
224 fdt_del_node_and_alias(blob, "rio0");
227 if (!is_serdes_configured(SRIO2)) {
228 fdt_del_node_and_alias(blob, "rio1");
231 fdt_del_node_and_alias(blob, "rio1");
235 void ft_board_setup(void *blob, bd_t *bd)
240 ft_cpu_setup(blob, bd);
244 base = getenv_bootm_low();
245 size = getenv_bootm_size();
247 fdt_fixup_memory(blob, (u64)base, (u64)size);
250 pci_of_setup(blob, bd);
253 fdt_fixup_liodn(blob);
256 int board_eth_init(bd_t *bis)
258 return pci_eth_init(bis);