1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 struct fsl_e_tlb_entry tlb_table[] = {
13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
15 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
25 0, 0, BOOKE_PAGESZ_4K, 0),
26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
29 0, 0, BOOKE_PAGESZ_4K, 0),
31 SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
32 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
33 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
38 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
39 0, 0, BOOKE_PAGESZ_4K, 0),
43 /* *I*** - Covers boot page */
44 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
46 #if !defined(CONFIG_NXP_ESBC)
48 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
49 * SRAM is at 0xfff00000, it covered the 0xfffff000.
51 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
52 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
53 0, 0, BOOKE_PAGESZ_1M, 1),
56 * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
57 * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
58 * and virtual address is CONFIG_SYS_MONITOR_BASE
61 SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
62 CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 0, 0, BOOKE_PAGESZ_1M, 1),
67 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
69 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
70 * space is at 0xfff00000, it covered the 0xfffff000.
72 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
73 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
75 0, 0, BOOKE_PAGESZ_1M, 1),
77 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
79 0, 0, BOOKE_PAGESZ_4K, 1),
83 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
84 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, 1, BOOKE_PAGESZ_16M, 1),
87 /* *I*G* - Flash, localbus */
88 /* This will be changed to *I*G* after relocation to RAM. */
89 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
90 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
91 0, 2, BOOKE_PAGESZ_256M, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
95 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
96 0, 3, BOOKE_PAGESZ_1G, 1),
99 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
100 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
101 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
102 0, 4, BOOKE_PAGESZ_256M, 1),
104 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
105 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
106 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
107 0, 5, BOOKE_PAGESZ_256M, 1),
109 /* *I*G* - PCI I/O */
110 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
111 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
112 0, 6, BOOKE_PAGESZ_256K, 1),
115 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
116 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
118 0, 9, BOOKE_PAGESZ_1M, 1),
119 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
120 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
121 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
122 0, 10, BOOKE_PAGESZ_1M, 1),
124 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
125 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
127 0, 11, BOOKE_PAGESZ_1M, 1),
128 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
129 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
130 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
131 0, 12, BOOKE_PAGESZ_1M, 1),
133 #ifdef CONFIG_SYS_DCSRBAR_PHYS
134 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
135 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
136 0, 13, BOOKE_PAGESZ_4M, 1),
138 #ifdef CONFIG_SYS_NAND_BASE
141 * entry 14 and 15 has been used hard coded, they will be disabled
142 * in cpu_init_f, so we use entry 16 for nand.
144 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
145 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
146 0, 16, BOOKE_PAGESZ_1M, 1),
148 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
150 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
151 * fetching ucode and ENV from master
153 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
154 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
155 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
156 0, 17, BOOKE_PAGESZ_1M, 1),
160 int num_tlb_entries = ARRAY_SIZE(tlb_table);