2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/immap_85xx.h>
11 #include "../../../drivers/qe/qe.h"
14 DECLARE_GLOBAL_DATA_PTR;
16 void __weak board_mem_sleep_setup(void)
20 void __weak board_sleep_prepare(void)
24 bool is_warm_boot(void)
26 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
28 if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
34 void fsl_dp_disable_console(void)
36 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
40 * When wakeup from deep sleep, the first 128 bytes space
41 * will be used to do DDR training which corrupts the data
42 * in there. This function will restore them.
44 static void dp_ddr_restore(void)
46 volatile u64 *src, *dst;
48 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
50 /* get the address of ddr date from SPARECR3 */
51 src = (u64 *)in_be32(&scfg->sparecr[2]);
52 dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
54 for (i = 0; i < DDR_BUFF_LEN / 8; i++)
60 static void dp_resume_prepare(void)
64 board_sleep_prepare();
67 #if defined(CONFIG_RAMBOOT_PBL)
78 int fsl_dp_resume(void)
81 void (*kernel_resume)(void);
82 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
89 /* Get the entry address and jump to kernel */
90 start_addr = in_be32(&scfg->sparecr[1]);
91 debug("Entry address is 0x%08x\n", start_addr);
92 kernel_resume = (void (*)(void))start_addr;