Merge git://git.denx.de/u-boot-sunxi
[oweals/u-boot.git] / board / freescale / common / idt8t49n222a_serdes_clk.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2013 Freescale Semiconductor, Inc.
4  * Author: Shaveta Leekha <shaveta@freescale.com>
5  */
6
7 #ifndef __IDT8T49N222A_SERDES_CLK_H_
8 #define __IDT8T49N222A_SERDES_CLK_H_    1
9
10 #include <common.h>
11 #include <i2c.h>
12 #include "qixis.h"
13 #include "../b4860qds/b4860qds_qixis.h"
14 #include <errno.h>
15
16 #define NUM_IDT_REGS            23
17 #define NUM_IDT_REGS_FEEDBACK   12
18 #define NUM_IDT_REGS_156_25     11
19
20 /* CLK */
21 enum serdes_refclk {
22         SERDES_REFCLK_100,      /* refclk 100Mhz */
23         SERDES_REFCLK_122_88,   /* refclk 122.88Mhz */
24         SERDES_REFCLK_125,      /* refclk 125Mhz */
25         SERDES_REFCLK_156_25,   /* refclk 156.25Mhz */
26         SERDES_REFCLK_NONE = -1,
27 };
28
29 /* configuration values for IDT registers for Output Refclks:
30  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
31  */
32 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
33                 {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
34                 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
35                 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
36                 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
37                 {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
38                 {0x16, 0xA0} };
39
40
41 /* configuration values for IDT registers for Output Refclks:
42  * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
43  */
44 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
45                 {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
46                 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
47                 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
48                 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
49                 {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
50                 {0x16, 0xA0} };
51
52 /* Reconfiguration values for some of IDT registers for
53  * Output Refclks:
54  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
55  * and with feedback as 1
56  */
57 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
58                 {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
59                 {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
60                 {0x14, 0x00}, {0x15, 0xE8} };
61
62 /* configuration values for IDT registers for Output Refclks:
63  * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
64  */
65 static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
66                 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
67                 {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
68                 {0x15, 0xE8} };
69
70 /* configuration values for IDT registers for Output Refclks:
71  * Refclk1 : 100MHz Refclk2 : 156.25MHz
72  */
73 static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
74                 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
75                 {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
76                 {0x15, 0xE8} };
77
78 /* configuration values for IDT registers for Output Refclks:
79  * Refclk1 : 125MHz Refclk2 : 156.25MHz
80  */
81 static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
82                 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
83                 {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
84                 {0x15, 0xE8} };
85
86 /* configuration values for IDT registers for Output Refclks:
87  * Refclk1 : 156.25MHz Refclk2 : 100MHz
88  */
89 static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
90                 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
91                 {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
92                 {0x15, 0xE8} };
93
94 /* configuration values for IDT registers for Output Refclks:
95  * Refclk1 : 156.25MHz Refclk2 : 125MHz
96  */
97 static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
98                 {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
99                 {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
100                 {0x15, 0xE8} };
101
102 int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
103                         enum serdes_refclk refclk1,
104                         enum serdes_refclk refclk2, u8 feedback);
105
106 #endif  /*__IDT8T49N222A_SERDES_CLK_H_ */