board/freescale/bsc9132qds/ddr.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/mmu.h>
   9 #include <asm/immap_85xx.h>
  10 #include <asm/processor.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <fsl_ddr_dimm_params.h>
  13 #include <asm/io.h>
  14 #include <asm/fsl_law.h>
  15
  16 #ifndef CONFIG_SYS_DDR_RAW_TIMING
  17
  18 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  19         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  20         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  21         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  22         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  23         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  24         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  25         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  26         .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  27         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  28         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  29         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  30         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  31         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  32         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  33         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  34         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  35         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  36         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  37         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  38         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  39         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
  40         .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  41         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  42         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  43 };
  44
  45 fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
  46         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  47         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  48         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  49         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
  50         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
  51         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
  52         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
  53         .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  54         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  55         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
  56         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
  57         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  58         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
  59         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  60         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
  61         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  62         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  63         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  64         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  65         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  66         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
  67         .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  68         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  69         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  70 };
  71
  72
  73 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  74         {750, 850, &ddr_cfg_regs_800},
  75         {1060, 1333, &ddr_cfg_regs_1333},
  76         {0, 0, NULL}
  77 };
  78
  79 /*
  80  * Fixed sdram init -- doesn't use serial presence detect.
  81  */
  82 phys_size_t fixed_sdram(void)
  83 {
  84         int i;
  85         char buf[32];
  86         fsl_ddr_cfg_regs_t ddr_cfg_regs;
  87         phys_size_t ddr_size;
  88         ulong ddr_freq, ddr_freq_mhz;
  89
  90         ddr_freq = get_ddr_freq(0);
  91         ddr_freq_mhz = ddr_freq / 1000000;
  92
  93         printf("Configuring DDR for %s MT/s data rate\n",
  94                                 strmhz(buf, ddr_freq));
  95
  96         for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  97                 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  98                    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  99                         memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
 100                                                         sizeof(ddr_cfg_regs));
 101                         break;
 102                 }
 103         }
 104
 105         if (fixed_ddr_parm_0[i].max_freq == 0)
 106                 panic("Unsupported DDR data rate %s MT/s data rate\n",
 107                                         strmhz(buf, ddr_freq));
 108
 109         ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 110         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 111
 112         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
 113                                         LAW_TRGT_IF_DDR_1) < 0) {
 114                 printf("ERROR setting Local Access Windows for DDR\n");
 115                 return 0;
 116         }
 117
 118         return ddr_size;
 119 }
 120
 121 #else /* CONFIG_SYS_DDR_RAW_TIMING */
 122 /* Micron MT41J512M8_187E */
 123 dimm_params_t ddr_raw_timing = {
 124         .n_ranks = 1,
 125         .rank_density = 1073741824u,
 126         .capacity = 1073741824u,
 127         .primary_sdram_width = 32,
 128         .ec_sdram_width = 0,
 129         .registered_dimm = 0,
 130         .mirrored_dimm = 0,
 131         .n_row_addr = 15,
 132         .n_col_addr = 10,
 133         .n_banks_per_sdram_device = 8,
 134         .edc_config = 0,
 135         .burst_lengths_bitmask = 0x0c,
 136
 137         .tckmin_x_ps = 1870,
 138         .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
 139         .taa_ps = 13125,
 140         .twr_ps = 15000,
 141         .trcd_ps = 13125,
 142         .trrd_ps = 7500,
 143         .trp_ps = 13125,
 144         .tras_ps = 37500,
 145         .trc_ps = 50625,
 146         .trfc_ps = 160000,
 147         .twtr_ps = 7500,
 148         .trtp_ps = 7500,
 149         .refresh_rate_ps = 7800000,
 150         .tfaw_ps = 37500,
 151 };
 152
 153 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 154                 unsigned int controller_number,
 155                 unsigned int dimm_number)
 156 {
 157         const char dimm_model[] = "Fixed DDR on board";
 158
 159         if ((controller_number == 0) && (dimm_number == 0)) {
 160                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 161                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 162                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 163         }
 164
 165         return 0;
 166 }
 167
 168 void fsl_ddr_board_options(memctl_options_t *popts,
 169                                 dimm_params_t *pdimm,
 170                                 unsigned int ctrl_num)
 171 {
 172         int i;
 173         popts->clk_adjust = 6;
 174         popts->cpo_override = 0x1f;
 175         popts->write_data_delay = 2;
 176         popts->half_strength_driver_enable = 1;
 177         /* Write leveling override */
 178         popts->wrlvl_en = 1;
 179         popts->wrlvl_override = 1;
 180         popts->wrlvl_sample = 0xf;
 181         popts->wrlvl_start = 0x8;
 182         popts->trwt_override = 1;
 183         popts->trwt = 0;
 184
 185         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 186                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 187                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 188         }
 189 }
 190
 191 #endif /* CONFIG_SYS_DDR_RAW_TIMING */