1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
8 #include <asm/processor.h>
10 #include <asm/cache.h>
11 #include <asm/immap_85xx.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
24 #include <fsl_ddr_sdram.h>
25 #include <jffs2/load_kernel.h>
31 #include <asm/fsl_pci.h>
34 #include "../common/qixis.h"
35 DECLARE_GLOBAL_DATA_PTR;
38 int board_early_init_f(void)
40 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
42 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
47 void board_config_serdes_mux(void)
49 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 u32 pordevsr = in_be32(&gur->pordevsr);
51 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
52 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
55 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
66 QIXIS_WRITE_I2C(brdcfg[4], 0x03);
69 /* PEX(1) PEX(2) SGMII1 CPRI 1 */
80 QIXIS_WRITE_I2C(brdcfg[4], 0x01);
83 /* PEX(1) PEX(2) SGMII1 SGMII2 */
86 QIXIS_WRITE_I2C(brdcfg[4], 0x00);
89 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
100 QIXIS_WRITE_I2C(brdcfg[4], 0x07);
103 /* PEX(1) SGMII2 SGMII1 CPRI 1 */
114 QIXIS_WRITE_I2C(brdcfg[4], 0x05);
117 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
123 QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
132 /* Configure DSP DDR controller */
133 void dsp_ddr_configure(void)
136 *There are separate DDR-controllers for DSP and PowerPC side DDR.
137 *copy the ddr controller settings from PowerPC side DDR controller
138 *to the DSP DDR controller as connected DDR memories are similar.
140 struct ccsr_ddr __iomem *pa_ddr =
141 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
142 struct ccsr_ddr temp_ddr;
143 struct ccsr_ddr __iomem *dsp_ddr =
144 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
146 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
147 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
148 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
149 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
150 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
153 int board_early_init_r(void)
155 #ifdef CONFIG_MTD_NOR_FLASH
156 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
157 int flash_esel = find_tlb_idx((void *)flashbase, 1);
160 * Remap Boot flash region to caching-inhibited
161 * so that flash can be erased properly.
164 /* Flush d-cache and invalidate i-cache of any FLASH data */
168 if (flash_esel == -1) {
169 /* very unlikely unless something is messed up */
170 puts("Error: Could not find TLB for FLASH BASE\n");
171 flash_esel = 2; /* give our best effort to continue */
173 /* invalidate existing TLB entry for flash */
174 disable_tlb(flash_esel);
177 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
178 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
179 0, flash_esel, BOOKE_PAGESZ_64M, 1);
181 set_tlb(1, flashbase + 0x4000000,
182 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
183 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
184 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
186 board_config_serdes_mux();
192 void pci_init_board(void)
194 fsl_pcie_init_board(0);
196 #endif /* ifdef CONFIG_PCI */
200 struct cpu_type *cpu;
204 printf("Board: %sQDS\n", cpu->name);
206 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
207 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
209 sw = QIXIS_READ(brdcfg[0]);
210 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
212 printf("IFC chip select:");
224 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
231 int board_eth_init(bd_t *bis)
233 #ifdef CONFIG_TSEC_ENET
234 struct fsl_pq_mdio_info mdio_info;
235 struct tsec_info_struct tsec_info[4];
239 SET_STD_TSEC_INFO(tsec_info[num], 1);
245 SET_STD_TSEC_INFO(tsec_info[num], 2);
249 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
250 mdio_info.name = DEFAULT_MII_NAME;
252 fsl_pq_mdio_init(bis, &mdio_info);
253 tsec_eth_init(bis, tsec_info, num);
263 #define USBMUX_SEL_MASK 0xc0
264 #define USBMUX_SEL_UART2 0xc0
265 #define USBMUX_SEL_USB 0x40
266 #define SPIMUX_SEL_UART3 0x80
267 #define GPS_MUX_SEL_GPS 0x40
269 #define TSEC_1588_CLKIN_MASK 0x03
270 #define CON_XCVR_REF_CLK 0x00
272 int misc_init_r(void)
275 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
276 u32 porbmsr = in_be32(&gur->porbmsr);
277 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
279 /*Configure 1588 clock-in source from RF Card*/
280 val = QIXIS_READ_I2C(brdcfg[5]);
281 QIXIS_WRITE_I2C(brdcfg[5],
282 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
284 if (hwconfig("uart2") && hwconfig("usb1")) {
285 printf("UART2 and USB cannot work together on the board\n");
286 printf("Remove one from hwconfig and reset\n");
288 if (hwconfig("uart2")) {
289 val = QIXIS_READ_I2C(brdcfg[5]);
290 QIXIS_WRITE_I2C(brdcfg[5],
291 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
292 clrbits_be32(&gur->pmuxcr3,
293 MPC85xx_PMUXCR3_USB_SEL_MASK);
294 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
296 /* By default USB should be selected.
297 * Programming FPGA to select USB. */
298 val = QIXIS_READ_I2C(brdcfg[5]);
299 QIXIS_WRITE_I2C(brdcfg[5],
300 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
305 if (hwconfig("sim")) {
306 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
307 romloc == PORBMSR_ROMLOC_NOR ||
308 romloc == PORBMSR_ROMLOC_SPI) {
310 val = QIXIS_READ_I2C(brdcfg[3]);
311 QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
312 clrbits_be32(&gur->pmuxcr,
313 MPC85xx_PMUXCR0_SIM_SEL_MASK);
314 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
318 if (hwconfig("uart3")) {
319 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
320 romloc == PORBMSR_ROMLOC_NOR ||
321 romloc == PORBMSR_ROMLOC_SDHC) {
323 /* UART3 and SPI1 (Flashes) are muxed together */
324 val = QIXIS_READ_I2C(brdcfg[3]);
325 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
326 clrbits_be32(&gur->pmuxcr3,
327 MPC85xx_PMUXCR3_UART3_SEL_MASK);
328 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
330 /* MUX to select UART3 connection to J24 header
332 val = QIXIS_READ_I2C(brdcfg[6]);
334 QIXIS_WRITE_I2C(brdcfg[6],
335 (val | GPS_MUX_SEL_GPS));
337 QIXIS_WRITE_I2C(brdcfg[6],
338 (val & ~(GPS_MUX_SEL_GPS)));
344 void fdt_del_node_compat(void *blob, const char *compatible)
347 int off = fdt_node_offset_by_compatible(blob, -1, compatible);
349 printf("WARNING: could not find compatible node %s: %s.\n",
350 compatible, fdt_strerror(off));
353 err = fdt_del_node(blob, off);
355 printf("WARNING: could not remove %s: %s.\n",
356 compatible, fdt_strerror(err));
360 #if defined(CONFIG_OF_BOARD_SETUP)
361 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
362 static const struct node_info nodes[] = {
363 { "cfi-flash", MTD_DEV_TYPE_NOR, },
364 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
367 int ft_board_setup(void *blob, bd_t *bd)
372 ft_cpu_setup(blob, bd);
374 base = env_get_bootm_low();
375 size = env_get_bootm_size();
377 #if defined(CONFIG_PCI)
381 fdt_fixup_memory(blob, (u64)base, (u64)size);
382 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
383 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
386 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
387 u32 porbmsr = in_be32(&gur->porbmsr);
388 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
390 if (!(hwconfig("uart2") && hwconfig("usb1"))) {
391 /* If uart2 is there in hwconfig remove usb node from
394 if (hwconfig("uart2")) {
395 /* remove dts usb node */
396 fdt_del_node_compat(blob, "fsl-usb2-dr");
398 fsl_fdt_fixup_dr_usb(blob, bd);
399 fdt_del_node_and_alias(blob, "serial2");
403 if (hwconfig("uart3")) {
404 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
405 romloc == PORBMSR_ROMLOC_NOR ||
406 romloc == PORBMSR_ROMLOC_SDHC)
407 /* Delete SPI node from the device tree */
408 fdt_del_node_and_alias(blob, "spi1");
410 fdt_del_node_and_alias(blob, "serial3");
412 if (hwconfig("sim")) {
413 if (romloc == PORBMSR_ROMLOC_NAND_2K ||
414 romloc == PORBMSR_ROMLOC_NOR ||
415 romloc == PORBMSR_ROMLOC_SPI) {
417 /* remove dts sdhc node */
418 fdt_del_node_compat(blob, "fsl,esdhc");
419 } else if (romloc == PORBMSR_ROMLOC_SDHC) {
421 /* remove dts sim node */
422 fdt_del_node_compat(blob, "fsl,sim-v1.0");
423 printf("SIM & SDHC can't work together on the board");
424 printf("\nRemove sim from hwconfig and reset\n");