1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
9 struct fsl_e_tlb_entry tlb_table[] = {
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
12 MAS3_SX|MAS3_SW|MAS3_SR, 0,
13 0, 0, BOOKE_PAGESZ_4K, 0),
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
28 /* *I*** - Covers boot page */
29 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
30 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
31 0, 0, BOOKE_PAGESZ_4K, 1),
32 #ifdef CONFIG_SPL_NAND_BOOT
33 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
35 0, 10, BOOKE_PAGESZ_4K, 1),
38 /* *I*G* - CCSRBAR (PA) */
39 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 1, BOOKE_PAGESZ_1M, 1),
44 SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
45 CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
46 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
47 0, 2, BOOKE_PAGESZ_1M, 1),
49 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
50 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
52 0, 8, BOOKE_PAGESZ_1G, 1),
55 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 3, BOOKE_PAGESZ_1M, 1)
61 int num_tlb_entries = ARRAY_SIZE(tlb_table);