1 /* Copyright 2013 Freescale Semiconductor, Inc.
3 * SPDX-License-Identifier: GPL-2.0+
12 #include "../common/qixis.h"
13 #include "b4860qds_qixis.h"
15 DECLARE_GLOBAL_DATA_PTR;
17 phys_size_t get_effective_memsize(void)
19 return CONFIG_SYS_L3_SIZE;
22 unsigned long get_board_sys_clk(void)
24 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
26 switch ((sysclk_conf & 0x0C) >> 2) {
37 unsigned long get_board_ddr_clk(void)
39 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
41 switch (ddrclk_conf & 0x03) {
52 void board_init_f(ulong bootflag)
54 u32 plat_ratio, sys_clk, uart_clk;
55 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
57 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
58 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
60 /* Update GD pointer */
61 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
63 /* compiler optimization barrier needed for GCC >= 3.4 */
64 __asm__ __volatile__("" : : : "memory");
68 /* initialize selected port with appropriate baud rate */
69 sys_clk = get_board_sys_clk();
70 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
71 uart_clk = sys_clk * plat_ratio / 2;
73 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
74 uart_clk / 16 / CONFIG_BAUDRATE);
76 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
79 void board_init_r(gd_t *gd, ulong dest_addr)
83 bd = (bd_t *)(gd + sizeof(gd_t));
84 memset(bd, 0, sizeof(bd_t));
86 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
87 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
91 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
92 CONFIG_SPL_RELOC_MALLOC_SIZE);
94 #ifndef CONFIG_SPL_NAND_BOOT
98 /* relocate environment function pointers etc. */
99 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
100 (uchar *)CONFIG_ENV_ADDR);
101 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
109 gd->ram_size = initdram(0);
111 #ifdef CONFIG_SPL_NAND_BOOT