2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/errno.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
24 #include "../common/qixis.h"
25 #include "../common/vsc3316_3308.h"
26 #include "../common/idt8t49n222a_serdes_clk.h"
27 #include "../common/zm7300.h"
29 #include "b4860qds_qixis.h"
30 #include "b4860qds_crossbar_con.h"
32 #define CLK_MUX_SEL_MASK 0x4
33 #define ETH_PHY_CLK_OUT 0x4
35 DECLARE_GLOBAL_DATA_PTR;
41 struct cpu_type *cpu = gd->arch.cpu;
42 static const char *const freq[] = {"100", "125", "156.25", "161.13",
43 "122.88", "122.88", "122.88"};
46 printf("Board: %sQDS, ", cpu->name);
47 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
48 QIXIS_READ(id), QIXIS_READ(arch));
50 sw = QIXIS_READ(brdcfg[0]);
51 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
54 printf("vBank: %d\n", sw);
55 else if (sw >= 0x8 && sw <= 0xE)
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
60 printf("FPGA: v%d (%s), build %d",
61 (int)QIXIS_READ(scver), qixis_read_tag(buf),
62 (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf));
67 * Display the actual SERDES reference clocks as configured by the
68 * dip switches on the board. Note that the SWx registers could
69 * technically be set to force the reference clocks to match the
70 * values that the SERDES expects (or vice versa). For now, however,
71 * we just display both values and hope the user notices when they
74 puts("SERDES Reference Clocks: ");
75 sw = QIXIS_READ(brdcfg[2]);
76 clock = (sw >> 5) & 7;
77 printf("Bank1=%sMHz ", freq[clock]);
78 sw = QIXIS_READ(brdcfg[4]);
79 clock = (sw >> 6) & 3;
80 printf("Bank2=%sMHz\n", freq[clock]);
85 int select_i2c_ch_pca(u8 ch)
89 /* Selecting proper channel via PCA*/
90 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
92 printf("PCA: failed to select proper channel.\n");
100 * read_voltage from sensor on I2C bus
101 * We use average of 4 readings, waiting for 532us befor another reading
103 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
104 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
106 static inline int read_voltage(void)
108 int i, ret, voltage_read = 0;
111 for (i = 0; i < NUM_READINGS; i++) {
112 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
113 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
115 printf("VID: failed to read core voltage\n");
118 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
119 printf("VID: Core voltage sensor error\n");
122 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
124 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
125 udelay(WAIT_FOR_ADC);
127 /* calculate the average */
128 voltage_read /= NUM_READINGS;
133 static int adjust_vdd(ulong vdd_override)
135 int re_enable = disable_interrupts();
136 ccsr_gur_t __iomem *gur =
137 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
140 int vdd_target, vdd_last;
141 int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
143 unsigned int orig_i2c_speed;
144 unsigned long vdd_string_override;
146 static const uint16_t vdd[32] = {
179 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
181 printf("VID: I2c failed to switch channel\n");
186 /* get the voltage ID from fuse status register */
187 fusesr = in_be32(&gur->dcfg_fusesr);
188 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
189 FSL_CORENET_DCFG_FUSESR_VID_MASK;
190 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
191 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
192 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
194 vdd_target = vdd[vid];
195 debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
198 /* check override variable for overriding VDD */
199 vdd_string = getenv("b4qds_vdd_mv");
200 if (vdd_override == 0 && vdd_string &&
201 !strict_strtoul(vdd_string, 10, &vdd_string_override))
202 vdd_override = vdd_string_override;
203 if (vdd_override >= 819 && vdd_override <= 1212) {
204 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
205 debug("VDD override is %lu\n", vdd_override);
206 } else if (vdd_override != 0) {
207 printf("Invalid value.\n");
210 if (vdd_target == 0) {
211 printf("VID: VID not used\n");
217 * Read voltage monitor to check real voltage.
218 * Voltage monitor LSB is 4mv.
220 vdd_last = read_voltage();
222 printf("VID: abort VID adjustment\n");
227 debug("VID: Core voltage is at %d mV\n", vdd_last);
228 ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
230 printf("VID: I2c failed to switch channel to DPM\n");
235 /* Round up to the value of step of Voltage regulator */
236 voltage = roundup(vdd_target, ZM_STEP);
237 debug("VID: rounded up voltage = %d\n", voltage);
239 /* lower the speed to 100kHz to access ZM7300 device */
240 debug("VID: Setting bus speed to 100KHz if not already set\n");
241 orig_i2c_speed = i2c_get_bus_speed();
242 if (orig_i2c_speed != 100000)
243 i2c_set_bus_speed(100000);
245 /* Read the existing level on board, if equal to requsted one,
247 existing_voltage = zm_read_voltage();
249 /* allowing the voltage difference of one step 0.0125V acceptable */
250 if ((existing_voltage >= voltage) &&
251 (existing_voltage < (voltage + ZM_STEP))) {
252 debug("VID: voltage already set as requested,returning\n");
253 ret = existing_voltage;
256 debug("VID: Changing voltage for board from %dmV to %dmV\n",
257 existing_voltage/10, voltage/10);
259 if (zm_disable_wp() < 0) {
263 /* Change Voltage: the change is done through all the steps in the
264 way, to avoid reset to the board due to power good signal fail
265 in big voltage change gap jump.
267 if (existing_voltage > voltage) {
268 temp_voltage = existing_voltage - ZM_STEP;
269 while (temp_voltage >= voltage) {
270 ret = zm_write_voltage(temp_voltage);
271 if (ret == temp_voltage) {
272 temp_voltage -= ZM_STEP;
274 /* ZM7300 device failed to set
277 ("VID:Stepping down vol failed:%dmV\n",
284 temp_voltage = existing_voltage + ZM_STEP;
285 while (temp_voltage < (voltage + ZM_STEP)) {
286 ret = zm_write_voltage(temp_voltage);
287 if (ret == temp_voltage) {
288 temp_voltage += ZM_STEP;
290 /* ZM7300 device failed to set
293 ("VID:Stepping up vol failed:%dmV\n",
301 if (zm_enable_wp() < 0)
304 /* restore the speed to 400kHz */
305 out: debug("VID: Restore the I2C bus speed to %dKHz\n",
306 orig_i2c_speed/1000);
307 i2c_set_bus_speed(orig_i2c_speed);
311 ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
313 printf("VID: I2c failed to switch channel\n");
317 vdd_last = read_voltage();
318 select_i2c_ch_pca(I2C_CH_DEFAULT);
321 printf("VID: Core voltage %d mV\n", vdd_last);
331 int configure_vsc3316_3308(void)
333 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
334 unsigned int num_vsc16_con, num_vsc08_con;
335 u32 serdes1_prtcl, serdes2_prtcl;
337 char buffer[HWCONFIG_BUFFER_SIZE];
340 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
341 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
342 if (!serdes1_prtcl) {
343 printf("SERDES1 is not enabled\n");
346 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
347 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
349 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
350 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
351 if (!serdes2_prtcl) {
352 printf("SERDES2 is not enabled\n");
355 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
356 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
358 switch (serdes1_prtcl) {
368 * Lanes: C,D,E,F,G,H: CPRI
370 debug("Configuring crossbar to use onboard SGMII PHYs:"
371 "srds_prctl:%x\n", serdes1_prtcl);
372 num_vsc16_con = NUM_CON_VSC3316;
373 /* Configure VSC3316 crossbar switch */
374 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
376 ret = vsc3316_config(VSC3316_TX_ADDRESS,
377 vsc16_tx_4sfp_sgmii_12_56,
381 ret = vsc3316_config(VSC3316_RX_ADDRESS,
382 vsc16_rx_4sfp_sgmii_12_56,
418 * Lanes: E,F,G,H: CPRI
420 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
421 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
422 num_vsc16_con = NUM_CON_VSC3316;
423 /* Configure VSC3316 crossbar switch */
424 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
426 ret = vsc3316_config(VSC3316_TX_ADDRESS,
427 vsc16_tx_sfp_sgmii_aurora,
431 ret = vsc3316_config(VSC3316_RX_ADDRESS,
432 vsc16_rx_sfp_sgmii_aurora,
441 #ifdef CONFIG_PPC_B4420
447 * Lanes: A,B,C,D: SGMII
448 * Lanes: E,F,G,H: CPRI
450 debug("Configuring crossbar to use onboard SGMII PHYs:"
451 "srds_prctl:%x\n", serdes1_prtcl);
452 num_vsc16_con = NUM_CON_VSC3316;
453 /* Configure VSC3316 crossbar switch */
454 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
456 ret = vsc3316_config(VSC3316_TX_ADDRESS,
457 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
460 ret = vsc3316_config(VSC3316_RX_ADDRESS,
461 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
474 num_vsc16_con = NUM_CON_VSC3316;
475 /* Configure VSC3316 crossbar switch */
476 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
478 ret = vsc3316_config(VSC3316_TX_ADDRESS,
479 vsc16_tx_sfp, num_vsc16_con);
482 ret = vsc3316_config(VSC3316_RX_ADDRESS,
483 vsc16_rx_sfp, num_vsc16_con);
491 printf("WARNING:VSC crossbars programming not supported for:%x"
492 " SerDes1 Protocol.\n", serdes1_prtcl);
496 num_vsc08_con = NUM_CON_VSC3308;
497 /* Configure VSC3308 crossbar switch */
498 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
499 switch (serdes2_prtcl) {
500 #ifdef CONFIG_PPC_B4420
512 ret = vsc3308_config(VSC3308_TX_ADDRESS,
513 vsc08_tx_amc, num_vsc08_con);
516 ret = vsc3308_config(VSC3308_RX_ADDRESS,
517 vsc08_rx_amc, num_vsc08_con);
543 * Extract hwconfig from environment since environment
544 * is not setup properly yet
546 getenv_f("hwconfig", buffer, sizeof(buffer));
549 if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
550 "sfp_amc", "sfp", buf)) {
551 #ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
552 /* change default VSC3308 for XFI erratum */
553 ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
554 vsc08_tx_sfp, num_vsc08_con);
558 ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
559 vsc08_rx_sfp, num_vsc08_con);
563 ret = vsc3308_config(VSC3308_TX_ADDRESS,
564 vsc08_tx_sfp, num_vsc08_con);
568 ret = vsc3308_config(VSC3308_RX_ADDRESS,
569 vsc08_rx_sfp, num_vsc08_con);
574 ret = vsc3308_config(VSC3308_TX_ADDRESS,
575 vsc08_tx_amc, num_vsc08_con);
579 ret = vsc3308_config(VSC3308_RX_ADDRESS,
580 vsc08_rx_amc, num_vsc08_con);
590 printf("WARNING:VSC crossbars programming not supported for: %x"
591 " SerDes2 Protocol.\n", serdes2_prtcl);
598 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
602 /* Steps For SerDes PLLs reset and reconfiguration
603 * or PLL power-up procedure
605 debug("CALIBRATE PLL:%d\n", pll_num);
606 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
607 SRDS_RSTCTL_SDRST_B);
609 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
610 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
612 setbits_be32(&srds_regs->bank[pll_num].rstctl,
614 setbits_be32(&srds_regs->bank[pll_num].rstctl,
615 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
616 | SRDS_RSTCTL_SDRST_B));
620 /* Check whether PLL has been locked or not */
621 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
623 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
624 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
631 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
634 u32 fcap, dcbias, bcap, pllcr1, pllcr0;
636 if (calibrate_pll(srds_regs, pll_num)) {
638 /* Read fcap, dcbias and bcap value */
639 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
640 SRDS_PLLCR0_DCBIAS_OUT_EN);
641 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
643 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
644 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
646 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
647 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
648 SRDS_PLLCR0_DCBIAS_OUT_EN);
649 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
651 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
652 debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
654 if (fcap == 0 && bcap == 1) {
656 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
657 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
658 | SRDS_RSTCTL_SDRST_B));
659 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
660 SRDS_PLLCR1_BCAP_EN);
661 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
662 SRDS_PLLCR1_BCAP_OVD);
663 if (calibrate_pll(srds_regs, pll_num)) {
664 /*save the fcap, dcbias and bcap values*/
665 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
666 SRDS_PLLCR0_DCBIAS_OUT_EN);
667 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
669 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
670 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
671 & SRDS_PLLSR2_BCAP_EN;
672 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
673 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
674 SRDS_PLLCR0_DCBIAS_OUT_EN);
676 (&srds_regs->bank[pll_num].pllsr2) &
678 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
681 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
682 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
683 | SRDS_RSTCTL_SDRST_B));
684 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
685 SRDS_PLLCR1_BYP_CAL);
686 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
687 SRDS_PLLCR1_BCAP_EN);
688 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
689 SRDS_PLLCR1_BCAP_OVD);
690 /* change the fcap and dcbias to the saved
691 * values from Step 3 */
692 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
693 SRDS_PLLCR1_PLL_FCAP);
695 (&srds_regs->bank[pll_num].pllcr1)|
696 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
697 out_be32(&srds_regs->bank[pll_num].pllcr1,
699 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
700 SRDS_PLLCR0_DCBIAS_OVRD);
702 (&srds_regs->bank[pll_num].pllcr0)|
703 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
704 out_be32(&srds_regs->bank[pll_num].pllcr0,
706 ret = calibrate_pll(srds_regs, pll_num);
712 } else { /* Step 5 */
713 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
714 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
715 | SRDS_RSTCTL_SDRST_B));
717 /* Change the fcap, dcbias, and bcap to the
718 * values from Step 1 */
719 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
720 SRDS_PLLCR1_BYP_CAL);
721 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
722 SRDS_PLLCR1_PLL_FCAP);
723 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
724 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
725 out_be32(&srds_regs->bank[pll_num].pllcr1,
727 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
728 SRDS_PLLCR0_DCBIAS_OVRD);
729 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
730 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
731 out_be32(&srds_regs->bank[pll_num].pllcr0,
733 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
734 SRDS_PLLCR1_BCAP_EN);
735 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
736 SRDS_PLLCR1_BCAP_OVD);
737 ret = calibrate_pll(srds_regs, pll_num);
746 static int check_serdes_pll_locks(void)
748 serdes_corenet_t *srds1_regs =
749 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
750 serdes_corenet_t *srds2_regs =
751 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
754 debug("\nSerDes1 Lock check\n");
755 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
756 ret1 = check_pll_locks(srds1_regs, i);
758 printf("SerDes1, PLL:%d didnt lock\n", i);
762 debug("\nSerDes2 Lock check\n");
763 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
764 ret2 = check_pll_locks(srds2_regs, i);
766 printf("SerDes2, PLL:%d didnt lock\n", i);
774 int config_serdes1_refclks(void)
776 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
777 serdes_corenet_t *srds_regs =
778 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
779 u32 serdes1_prtcl, lane;
780 unsigned int flag_sgmii_aurora_prtcl = 0;
784 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
785 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
786 if (!serdes1_prtcl) {
787 printf("SERDES1 is not enabled\n");
790 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
791 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
793 /* To prevent generation of reset request from SerDes
794 * while changing the refclks, By setting SRDS_RST_MSK bit,
795 * SerDes reset event cannot cause a reset request
797 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
799 /* Reconfigure IDT idt8t49n222a device for CPRI to work
800 * For this SerDes1's Refclk1 and refclk2 need to be set
803 switch (serdes1_prtcl) {
831 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
832 " for srds_prctl:%x\n", serdes1_prtcl);
833 ret = select_i2c_ch_pca(I2C_CH_IDT);
835 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
836 SERDES_REFCLK_122_88,
837 SERDES_REFCLK_122_88, 0);
839 printf("IDT8T49N222A configuration failed.\n");
842 debug("IDT8T49N222A configured.\n");
846 select_i2c_ch_pca(I2C_CH_DEFAULT);
848 /* Change SerDes1's Refclk1 to 125MHz for on board
849 * SGMIIs or Aurora to work
851 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
852 enum srds_prtcl lane_prtcl = serdes_get_prtcl
853 (0, serdes1_prtcl, lane);
854 switch (lane_prtcl) {
855 case SGMII_FM1_DTSEC1:
856 case SGMII_FM1_DTSEC2:
857 case SGMII_FM1_DTSEC3:
858 case SGMII_FM1_DTSEC4:
859 case SGMII_FM1_DTSEC5:
860 case SGMII_FM1_DTSEC6:
862 flag_sgmii_aurora_prtcl++;
869 if (flag_sgmii_aurora_prtcl)
870 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
872 /* Steps For SerDes PLLs reset and reconfiguration after
873 * changing SerDes's refclks
875 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
876 debug("For PLL%d reset and reconfiguration after"
877 " changing refclks\n", i+1);
878 clrbits_be32(&srds_regs->bank[i].rstctl,
879 SRDS_RSTCTL_SDRST_B);
881 clrbits_be32(&srds_regs->bank[i].rstctl,
882 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
884 setbits_be32(&srds_regs->bank[i].rstctl,
886 setbits_be32(&srds_regs->bank[i].rstctl,
887 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
888 | SRDS_RSTCTL_SDRST_B));
892 printf("WARNING:IDT8T49N222A configuration not"
893 " supported for:%x SerDes1 Protocol.\n",
898 /* Clearing SRDS_RST_MSK bit as now
899 * SerDes reset event can cause a reset request
901 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
905 int config_serdes2_refclks(void)
907 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
908 serdes_corenet_t *srds2_regs =
909 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
914 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
915 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
916 if (!serdes2_prtcl) {
917 debug("SERDES2 is not enabled\n");
920 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
921 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
923 /* To prevent generation of reset request from SerDes
924 * while changing the refclks, By setting SRDS_RST_MSK bit,
925 * SerDes reset event cannot cause a reset request
927 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
929 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
930 * For this SerDes2's Refclk1 need to be set to 100MHz
932 switch (serdes2_prtcl) {
933 #ifdef CONFIG_PPC_B4420
941 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
943 ret = select_i2c_ch_pca(I2C_CH_IDT);
945 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
947 SERDES_REFCLK_156_25, 0);
949 printf("IDT8T49N222A configuration failed.\n");
952 debug("IDT8T49N222A configured.\n");
956 select_i2c_ch_pca(I2C_CH_DEFAULT);
958 /* Steps For SerDes PLLs reset and reconfiguration after
959 * changing SerDes's refclks
961 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
962 clrbits_be32(&srds2_regs->bank[i].rstctl,
963 SRDS_RSTCTL_SDRST_B);
965 clrbits_be32(&srds2_regs->bank[i].rstctl,
966 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
968 setbits_be32(&srds2_regs->bank[i].rstctl,
970 setbits_be32(&srds2_regs->bank[i].rstctl,
971 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
972 | SRDS_RSTCTL_SDRST_B));
978 printf("IDT configuration not supported for:%x S2 Protocol.\n",
983 /* Clearing SRDS_RST_MSK bit as now
984 * SerDes reset event can cause a reset request
986 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
990 int board_early_init_r(void)
992 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
993 int flash_esel = find_tlb_idx((void *)flashbase, 1);
995 u32 svr = SVR_SOC_VER(get_svr());
997 /* Create law for MAPLE only for personalities having MAPLE */
998 if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
999 (svr == SVR_B4420) || (svr == SVR_B4220)) {
1000 set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
1005 * Remap Boot flash + PROMJET region to caching-inhibited
1006 * so that flash can be erased properly.
1009 /* Flush d-cache and invalidate i-cache of any FLASH data */
1011 invalidate_icache();
1013 if (flash_esel == -1) {
1014 /* very unlikely unless something is messed up */
1015 puts("Error: Could not find TLB for FLASH BASE\n");
1016 flash_esel = 2; /* give our best effort to continue */
1018 /* invalidate existing TLB entry for flash + promjet */
1019 disable_tlb(flash_esel);
1022 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
1023 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
1024 0, flash_esel, BOOKE_PAGESZ_256M, 1);
1027 #ifdef CONFIG_SYS_DPAA_QBMAN
1031 * Adjust core voltage according to voltage ID
1032 * This function changes I2C mux to channel 2.
1034 if (adjust_vdd(0) < 0)
1035 printf("Warning: Adjusting core voltage failed\n");
1037 /* SerDes1 refclks need to be set again, as default clks
1038 * are not suitable for CPRI and onboard SGMIIs to work
1040 * This function will set SerDes1's Refclk1 and refclk2
1041 * as per SerDes1 protocols
1043 if (config_serdes1_refclks())
1044 printf("SerDes1 Refclks couldn't set properly.\n");
1046 printf("SerDes1 Refclks have been set.\n");
1048 /* SerDes2 refclks need to be set again, as default clks
1049 * are not suitable for PCIe SATA to work
1050 * This function will set SerDes2's Refclk1 and refclk2
1051 * for SerDes2 protocols having PCIe in them
1052 * for PCIe SATA to work
1054 ret = config_serdes2_refclks();
1056 printf("SerDes2 Refclks have been set.\n");
1057 else if (ret == -ENODEV)
1058 printf("SerDes disable, Refclks couldn't change.\n");
1060 printf("SerDes2 Refclk reconfiguring failed.\n");
1062 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
1063 defined(CONFIG_SYS_FSL_ERRATUM_A006475)
1064 /* Rechecking the SerDes locks after all SerDes configurations
1065 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
1066 * and at cold temperatures.
1067 * Following sequence ensure the proper locking of SerDes PLLs.
1069 if (SVR_MAJ(get_svr()) == 1) {
1070 if (check_serdes_pll_locks())
1071 printf("SerDes plls still not locked properly.\n");
1073 printf("SerDes plls have been locked well.\n");
1077 /* Configure VSC3316 and VSC3308 crossbar switches */
1078 if (configure_vsc3316_3308())
1079 printf("VSC:failed to configure VSC3316/3308.\n");
1081 printf("VSC:VSC3316/3308 successfully configured.\n");
1083 select_i2c_ch_pca(I2C_CH_DEFAULT);
1088 unsigned long get_board_sys_clk(void)
1090 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
1092 switch ((sysclk_conf & 0x0C) >> 2) {
1103 unsigned long get_board_ddr_clk(void)
1105 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
1107 switch (ddrclk_conf & 0x03) {
1118 static int serdes_refclock(u8 sw, u8 sdclk)
1125 brdcfg4 = QIXIS_READ(brdcfg[4]);
1126 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
1127 return SRDS_PLLCR0_RFCK_SEL_125;
1129 clock = (sw >> 5) & 7;
1131 clock = (sw >> 6) & 3;
1135 ret = SRDS_PLLCR0_RFCK_SEL_100;
1138 ret = SRDS_PLLCR0_RFCK_SEL_125;
1141 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
1144 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
1149 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
1159 #define NUM_SRDS_BANKS 2
1161 int misc_init_r(void)
1164 serdes_corenet_t *srds_regs =
1165 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
1166 u32 actual[NUM_SRDS_BANKS];
1170 sw = QIXIS_READ(brdcfg[2]);
1171 clock = serdes_refclock(sw, 1);
1175 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
1177 sw = QIXIS_READ(brdcfg[4]);
1178 clock = serdes_refclock(sw, 2);
1182 printf("Warning: SDREFCLK2 switch setting unsupported\n");
1184 for (i = 0; i < NUM_SRDS_BANKS; i++) {
1185 u32 pllcr0 = srds_regs->bank[i].pllcr0;
1186 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
1187 if (expected != actual[i]) {
1188 printf("Warning: SERDES bank %u expects reference clock"
1189 " %sMHz, but actual is %sMHz\n", i + 1,
1190 serdes_clock_to_string(expected),
1191 serdes_clock_to_string(actual[i]));
1198 int ft_board_setup(void *blob, bd_t *bd)
1203 ft_cpu_setup(blob, bd);
1205 base = getenv_bootm_low();
1206 size = getenv_bootm_size();
1208 fdt_fixup_memory(blob, (u64)base, (u64)size);
1211 pci_of_setup(blob, bd);
1214 fdt_fixup_liodn(blob);
1216 #ifdef CONFIG_HAS_FSL_DR_USB
1217 fdt_fixup_dr_usb(blob, bd);
1220 #ifdef CONFIG_SYS_DPAA_FMAN
1221 fdt_fixup_fman_ethernet(blob);
1222 fdt_fixup_board_enet(blob);
1229 * Dump board switch settings.
1230 * The bits that cannot be read/sampled via some FPGA or some
1231 * registers, they will be displayed as
1232 * underscore in binary format. mask[] has those bits.
1233 * Some bits are calculated differently than the actual switches
1234 * if booting with overriding by FPGA.
1236 void qixis_dump_switch(void)
1242 * Any bit with 1 means that bit cannot be reverse engineered.
1243 * It will be displayed as _ in binary format.
1245 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
1247 u8 brdcfg[16], dutcfg[16];
1249 for (i = 0; i < 16; i++) {
1250 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
1251 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
1254 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
1256 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
1257 ((dutcfg[2] & 0x07) << 4) | \
1258 ((dutcfg[6] & 0x10) >> 1) | \
1259 ((dutcfg[6] & 0x80) >> 5) | \
1260 ((dutcfg[1] & 0x40) >> 5) | \
1264 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
1265 ((brdcfg[1] & 0xc0) >> 2) | \
1268 puts("DIP switch settings:\n");
1269 for (i = 0; i < 5; i++) {
1270 printf("SW%d = 0b%s (0x%02x)\n",
1271 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);