2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
7 * SPDX-License-Identifier: GPL-2.0+
15 #define _NOT_USED_ 0xFFFFFFFF
17 /* ========================================================================= */
19 #ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
21 #if defined(CONFIG_DRAM_50MHZ)
23 static const uint dram_60ns[] =
24 { 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
25 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
26 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
27 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
28 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
29 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
30 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
31 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
32 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
33 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
34 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
35 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
36 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
37 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
38 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
39 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
41 static const uint dram_70ns[] =
42 { 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
43 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
44 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
45 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
46 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
47 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
48 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
51 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
52 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
53 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
54 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
55 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
59 static const uint edo_60ns[] =
60 { 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
61 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
62 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
63 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
64 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
69 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
70 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
73 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
77 static const uint edo_70ns[] =
78 { 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
79 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
80 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
81 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
82 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
83 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
85 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
87 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
88 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
91 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
92 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
93 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
95 #elif defined(CONFIG_DRAM_25MHZ)
99 static const uint dram_60ns[] =
100 { 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
101 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
102 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
103 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
104 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
105 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
106 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
107 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
108 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
109 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
110 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
117 static const uint dram_70ns[] =
118 { 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
121 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
122 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
123 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
124 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
127 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
128 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
132 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
133 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
135 static const uint edo_60ns[] =
136 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
138 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
139 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
140 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
141 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
142 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
143 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
144 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
145 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
146 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
147 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
148 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
149 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
150 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
151 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
153 static const uint edo_70ns[] =
154 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
155 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
156 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
157 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
158 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
159 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
160 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
161 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
162 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
163 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
164 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
165 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
166 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
167 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
168 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
169 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
171 #error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
174 /* ------------------------------------------------------------------------- */
175 static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
177 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
178 volatile memctl8xx_t *memctl = &immap->im_memctl;
185 upmconfig (UPMA, (uint *) edo_70ns,
186 sizeof (edo_70ns) / sizeof (uint));
188 upmconfig (UPMA, (uint *) dram_70ns,
189 sizeof (dram_70ns) / sizeof (uint));
196 upmconfig (UPMA, (uint *) edo_60ns,
197 sizeof (edo_60ns) / sizeof (uint));
199 upmconfig (UPMA, (uint *) dram_60ns,
200 sizeof (dram_60ns) / sizeof (uint));
209 memctl->memc_mptpr = 0x0400; /* divide by 16 */
212 case 4: /* 4 Mbyte uses only CS2 */
213 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
214 memctl->memc_or2 = 0xffc00800; /* 4M */
217 case 8: /* 8 Mbyte uses both CS3 and CS2 */
218 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
219 memctl->memc_or3 = 0xffc00800; /* 4M */
220 memctl->memc_br3 = 0x00400081 + base;
221 memctl->memc_or2 = 0xffc00800; /* 4M */
224 case 16: /* 16 Mbyte uses only CS2 */
225 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
226 memctl->memc_or2 = 0xff000800; /* 16M */
229 case 32: /* 32 Mbyte uses both CS3 and CS2 */
230 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
231 memctl->memc_or3 = 0xff000800; /* 16M */
232 memctl->memc_br3 = 0x01000081 + base;
233 memctl->memc_or2 = 0xff000800; /* 16M */
240 memctl->memc_br2 = 0x81 + base; /* use upma */
242 *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
244 /* if no dimm is inserted, noMbytes is still detected as 8m, so
245 * sanity check top and bottom of memory */
247 /* check bytes / 2 because get_ram_size tests at base+bytes, which
250 if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
251 *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
258 /* ------------------------------------------------------------------------- */
260 static void _dramdisable(void)
262 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
263 volatile memctl8xx_t *memctl = &immap->im_memctl;
265 memctl->memc_br2 = 0x00000000;
266 memctl->memc_br3 = 0x00000000;
268 /* maybe we should turn off upma here or something */
270 #endif /* !CONFIG_MPC885ADS */
272 /* ========================================================================= */
274 #ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
276 #if defined(CONFIG_SDRAM_100MHZ)
278 /* ------------------------------------------------------------------------- */
279 /* sdram table by Dan Malek */
281 /* This has the stretched early timing so the 50 MHz
282 * processor can make the 100 MHz timing. This will
283 * work at all processor speeds.
286 #ifdef SDRAM_ALT_INIT_SEQENCE
287 # define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
288 #define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
289 # define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */
290 # define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */
292 # define SDRAM_MxMR_PTx 195
293 # define UPM_MRS_ADDR 0x11
294 # define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */
295 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
297 static const uint sdram_table[] =
299 /* single read. (offset 0 in upm RAM) */
300 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
301 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
303 /* burst read. (offset 8 in upm RAM) */
304 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
305 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
308 /* precharge + MRS. (offset 11 in upm RAM) */
309 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
310 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
312 /* single write. (offset 18 in upm RAM) */
313 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
314 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316 /* burst write. (offset 20 in upm RAM) */
317 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
318 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
319 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
322 /* refresh. (offset 30 in upm RAM) */
323 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
324 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
325 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
327 /* exception. (offset 3c in upm RAM) */
328 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
330 #elif defined(CONFIG_SDRAM_50MHZ)
332 /* ------------------------------------------------------------------------- */
333 /* sdram table stolen from the fads manual */
334 /* for chip MB811171622A-100 */
336 /* this table is for 32-50MHz operation */
337 #ifdef SDRAM_ALT_INIT_SEQENCE
338 # define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
339 # define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
340 # define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */
341 # define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */
342 # define SDRAM_MPTRVALUE 0x400
343 #define SDRAM_MARVALUE 0x88
345 # define SDRAM_MxMR_PTx 128
346 # define UPM_MRS_ADDR 0x5
347 # define UPM_REFRESH_ADDR 0x30
348 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
350 static const uint sdram_table[] =
352 /* single read. (offset 0 in upm RAM) */
353 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
356 /* precharge + MRS. (offset 5 in upm RAM) */
357 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
359 /* burst read. (offset 8 in upm RAM) */
360 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
361 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
362 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
363 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
365 /* single write. (offset 18 in upm RAM) */
366 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
367 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
369 /* burst write. (offset 20 in upm RAM) */
370 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
371 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
372 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
373 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
375 /* refresh. (offset 30 in upm RAM) */
376 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
377 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
378 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
380 /* exception. (offset 3c in upm RAM) */
381 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
383 /* ------------------------------------------------------------------------- */
385 #error SDRAM not correctly configured
387 /* ------------------------------------------------------------------------- */
390 * Memory Periodic Timer Prescaler
393 #define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
394 #define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */
396 /* ------------------------------------------------------------------------- */
397 #ifdef SDRAM_ALT_INIT_SEQENCE
398 /* ------------------------------------------------------------------------- */
400 static int _initsdram(uint base, uint noMbytes)
402 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
403 volatile memctl8xx_t *memctl = &immap->im_memctl;
405 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
407 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
409 /* Configure the refresh (mostly). This needs to be
410 * based upon processor clock speed and optimized to provide
411 * the highest level of performance. For multiple banks,
412 * this time has to be divided by the number of banks.
413 * Although it is not clear anywhere, it appears the
414 * refresh steps through the chip selects for this UPM
415 * on each refresh cycle.
416 * We have to be careful changing
417 * UPM registers after we ask it to run these commands.
420 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
421 memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
425 /* Now run the precharge/nop/mrs commands.
428 memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
429 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
432 /* Run 8 refresh cycles */
434 memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/
435 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
439 memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */
440 memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */
441 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
445 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
447 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
448 memctl->memc_br4 = SDRAM_BR4VALUE | base;
453 /* ------------------------------------------------------------------------- */
454 #else /* !SDRAM_ALT_INIT_SEQUENCE */
455 /* ------------------------------------------------------------------------- */
457 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
458 # define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
459 # define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
461 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
462 # define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
463 # define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
466 * MxMR settings for SDRAM
470 # define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \
471 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
472 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
474 # define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \
475 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
476 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
478 static int _initsdram(uint base, uint noMbytes)
480 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
481 volatile memctl8xx_t *memctl = &immap->im_memctl;
483 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
485 memctl->memc_mptpr = MPTPR_2BK_4K;
486 memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
489 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
490 memctl->memc_br4 = SDRAM_BR4VALUE | base;
492 /* Perform SDRAM initilization */
493 # ifdef UPM_NOP_ADDR /* not currently in UPM table */
495 memctl->memc_mar = 0x00000000;
496 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
497 MCR_MLCF(0) | UPM_NOP_ADDR;
503 # ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
504 /* step 3: precharge */
505 memctl->memc_mar = 0x00000000;
506 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
507 MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
510 /* step 4: refresh */
511 memctl->memc_mar = 0x00000000;
512 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
513 MCR_MLCF(2) | UPM_REFRESH_ADDR;
516 * note: for some reason, the UPM values we are using include
521 memctl->memc_mar = 0x00000088;
522 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
523 MCR_MLCF(1) | UPM_MRS_ADDR;
526 memctl->memc_mar = 0x00000000;
527 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
528 MCR_MLCF(0) | UPM_NOP_ADDR;
534 memctl->memc_mbmr |= MBMR_PTBE;
537 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
539 /* ------------------------------------------------------------------------- */
541 static void _sdramdisable(void)
543 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
544 volatile memctl8xx_t *memctl = &immap->im_memctl;
546 memctl->memc_br4 = 0x00000000;
548 /* maybe we should turn off upmb here or something */
551 /* ------------------------------------------------------------------------- */
553 static int initsdram(uint base, uint *noMbytes)
555 uint m = CONFIG_SYS_SDRAM_SIZE>>20;
557 /* _initsdram needs access to sdram */
558 *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
560 if(!_initsdram(base, m))
567 *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
575 #endif /* CONFIG_FADS */
577 /* ========================================================================= */
579 phys_size_t initdram (int board_type)
581 uint sdramsz = 0; /* size of sdram in Mbytes */
582 uint m = 0; /* size of dram in Mbytes */
583 #ifndef CONFIG_MPC885ADS
584 uint base = 0; /* base of dram in bytes */
589 if (!initsdram (0x00000000, &sdramsz)) {
590 #ifndef CONFIG_MPC885ADS
591 base = sdramsz << 20;
593 printf ("(%u MB SDRAM) ", sdramsz);
596 #ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
597 k = (*((uint *) BCSR2) >> 23) & 0x0f;
600 /* "MCM36100 / MT8D132X" */
605 /* "MCM36800 / MT16D832X" */
609 /* "MCM36400 / MT8D432X" */
613 /* "MCM36200 / MT16D832X ?" */
630 printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
635 /* the FADS is missing this bit, all rams treated as non-edo */
638 s = (*((uint *) BCSR2) >> 27) & 0x01;
641 if (!_draminit (base, m, s, k)) {
642 printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
647 #endif /* !CONFIG_MPC885ADS */
648 m += sdramsz; /* add sdram size to total */
653 /* ------------------------------------------------------------------------- */
657 /* TODO: XXX XXX XXX */
658 printf ("test: 16 MB - ok\n");
663 /* ========================================================================= */
666 * Check Board Identity:
669 int checkboard (void)
671 #if defined(CONFIG_MPC86xADS)
672 puts ("Board: MPC86xADS\n");
673 #elif defined(CONFIG_MPC885ADS)
674 puts ("Board: MPC885ADS\n");
675 #else /* Only old ADS/FADS have got revision ID in BCSR3 */
676 uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
677 | (((*((uint *) BCSR3) >> 19) & 1) << 2)
678 | (((*((uint *) BCSR3) >> 16) & 3));
681 #if defined(CONFIG_FADS)
698 printf ("unknown (0x%x)\n", r);
701 #endif /* CONFIG_MPC86xADS */
706 /* ========================================================================= */
708 #if defined(CONFIG_CMD_PCMCIA)
710 #ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
711 volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
714 int pcmcia_init(void)
716 volatile pcmconf8xx_t *pcmp;
717 uint v, slota = 0, slotb = 0;
720 ** Enable the PCMCIA for a Flash card.
722 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
725 pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
726 pcmp->pcmc_por0 = 0xc00ff05d;
729 /* Set all slots to zero by default. */
730 pcmp->pcmc_pgcra = 0;
731 pcmp->pcmc_pgcrb = 0;
732 #ifdef CONFIG_PCMCIA_SLOT_A
733 pcmp->pcmc_pgcra = 0x40;
735 #ifdef CONFIG_PCMCIA_SLOT_B
736 pcmp->pcmc_pgcrb = 0x40;
739 /* enable PCMCIA buffers */
740 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
742 /* Check if any PCMCIA card is plugged in. */
744 #ifdef CONFIG_PCMCIA_SLOT_A
745 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
747 #ifdef CONFIG_PCMCIA_SLOT_B
748 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
751 if (!(slota || slotb)) {
752 printf("No card present\n");
753 pcmp->pcmc_pgcra = 0;
754 pcmp->pcmc_pgcrb = 0;
758 printf("Card present (");
762 /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
764 ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
768 #if defined(CONFIG_MPC86x)
769 switch ((pcmp->pcmc_pipr >> 30) & 3)
770 #elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
771 switch ((pcmp->pcmc_pipr >> 14) & 3)
781 v = 3; /* User lower voltage if supported! */
787 printf("5V, 3V and x.xV");
789 v = 3; /* User lower voltage if supported! */
799 printf("; using 3V");
801 ** Enable 3 volt Vcc.
803 *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
804 *((uint *)BCSR1) |= BCSR1_PCCVCC0;
808 printf("; using 5V");
811 ** Enable 5 volt Vcc.
813 *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
814 *((uint *)BCSR1) |= BCSR1_PCCVCC1;
819 *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
821 printf("; unknown voltage");
825 /* disable pcmcia reset after a while */
829 #ifdef CONFIG_PCMCIA_SLOT_A
830 pcmp->pcmc_pgcra = 0;
832 #ifdef CONFIG_PCMCIA_SLOT_B
833 pcmp->pcmc_pgcrb = 0;
836 /* If you using a real hd you should give a short
838 #ifdef CONFIG_DISK_SPINUP_TIME
839 udelay(CONFIG_DISK_SPINUP_TIME);
847 /* ========================================================================= */
849 #ifdef CONFIG_SYS_PC_IDE_RESET
851 void ide_set_reset(int on)
853 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
856 * Configure PC for IDE Reset Pin
858 if (on) { /* assert RESET */
859 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
860 } else { /* release RESET */
861 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
864 /* program port pin as GPIO output */
865 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
866 immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
867 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
870 #endif /* CONFIG_SYS_PC_IDE_RESET */