2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
7 * SPDX-License-Identifier: GPL-2.0+
15 #define _NOT_USED_ 0xFFFFFFFF
17 /* ========================================================================= */
19 #ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
21 #if defined(CONFIG_DRAM_50MHZ)
23 static const uint dram_60ns[] =
24 { 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
25 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
26 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
27 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
28 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
29 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
30 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
31 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
32 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
33 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
34 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
35 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
36 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
37 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
38 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
39 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
41 static const uint dram_70ns[] =
42 { 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
43 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
44 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
45 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
46 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
47 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
48 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
51 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
52 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
53 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
54 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
55 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
59 static const uint edo_60ns[] =
60 { 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
61 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
62 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
63 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
64 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
69 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
70 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
73 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
77 static const uint edo_70ns[] =
78 { 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
79 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
80 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
81 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
82 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
83 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
85 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
87 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
88 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
91 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
92 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
93 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
95 #elif defined(CONFIG_DRAM_25MHZ)
99 static const uint dram_60ns[] =
100 { 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
101 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
102 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
103 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
104 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
105 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
106 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
107 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
108 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
109 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
110 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
117 static const uint dram_70ns[] =
118 { 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
121 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
122 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
123 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
124 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
127 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
128 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
132 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
133 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
135 static const uint edo_60ns[] =
136 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
138 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
139 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
140 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
141 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
142 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
143 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
144 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
145 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
146 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
147 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
148 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
149 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
150 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
151 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
153 static const uint edo_70ns[] =
154 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
155 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
156 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
157 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
158 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
159 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
160 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
161 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
162 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
163 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
164 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
165 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
166 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
167 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
168 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
169 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
171 #error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
174 /* ------------------------------------------------------------------------- */
175 static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
177 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
178 volatile memctl8xx_t *memctl = &immap->im_memctl;
185 upmconfig (UPMA, (uint *) edo_70ns,
186 sizeof (edo_70ns) / sizeof (uint));
188 upmconfig (UPMA, (uint *) dram_70ns,
189 sizeof (dram_70ns) / sizeof (uint));
196 upmconfig (UPMA, (uint *) edo_60ns,
197 sizeof (edo_60ns) / sizeof (uint));
199 upmconfig (UPMA, (uint *) dram_60ns,
200 sizeof (dram_60ns) / sizeof (uint));
209 memctl->memc_mptpr = 0x0400; /* divide by 16 */
212 case 4: /* 4 Mbyte uses only CS2 */
214 memctl->memc_mamr = 0xc0a21114;
216 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
218 memctl->memc_or2 = 0xffc00800; /* 4M */
221 case 8: /* 8 Mbyte uses both CS3 and CS2 */
222 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
223 memctl->memc_or3 = 0xffc00800; /* 4M */
224 memctl->memc_br3 = 0x00400081 + base;
225 memctl->memc_or2 = 0xffc00800; /* 4M */
228 case 16: /* 16 Mbyte uses only CS2 */
229 #ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */
230 memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */
232 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
234 memctl->memc_or2 = 0xff000800; /* 16M */
237 case 32: /* 32 Mbyte uses both CS3 and CS2 */
238 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
239 memctl->memc_or3 = 0xff000800; /* 16M */
240 memctl->memc_br3 = 0x01000081 + base;
241 memctl->memc_or2 = 0xff000800; /* 16M */
248 memctl->memc_br2 = 0x81 + base; /* use upma */
250 *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
252 /* if no dimm is inserted, noMbytes is still detected as 8m, so
253 * sanity check top and bottom of memory */
255 /* check bytes / 2 because get_ram_size tests at base+bytes, which
258 if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
259 *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
266 /* ------------------------------------------------------------------------- */
268 static void _dramdisable(void)
270 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
271 volatile memctl8xx_t *memctl = &immap->im_memctl;
273 memctl->memc_br2 = 0x00000000;
274 memctl->memc_br3 = 0x00000000;
276 /* maybe we should turn off upma here or something */
278 #endif /* !CONFIG_MPC885ADS */
280 /* ========================================================================= */
282 #ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
284 #if defined(CONFIG_SDRAM_100MHZ)
286 /* ------------------------------------------------------------------------- */
287 /* sdram table by Dan Malek */
289 /* This has the stretched early timing so the 50 MHz
290 * processor can make the 100 MHz timing. This will
291 * work at all processor speeds.
294 #ifdef SDRAM_ALT_INIT_SEQENCE
295 # define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
296 #define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
297 # define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */
298 # define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */
300 # define SDRAM_MxMR_PTx 195
301 # define UPM_MRS_ADDR 0x11
302 # define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */
303 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
305 static const uint sdram_table[] =
307 /* single read. (offset 0 in upm RAM) */
308 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
309 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
311 /* burst read. (offset 8 in upm RAM) */
312 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
313 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
316 /* precharge + MRS. (offset 11 in upm RAM) */
317 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
318 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 /* single write. (offset 18 in upm RAM) */
321 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
322 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
324 /* burst write. (offset 20 in upm RAM) */
325 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
326 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
327 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
328 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
330 /* refresh. (offset 30 in upm RAM) */
331 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
332 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
333 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
335 /* exception. (offset 3c in upm RAM) */
336 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
338 #elif defined(CONFIG_SDRAM_50MHZ)
340 /* ------------------------------------------------------------------------- */
341 /* sdram table stolen from the fads manual */
342 /* for chip MB811171622A-100 */
344 /* this table is for 32-50MHz operation */
345 #ifdef SDRAM_ALT_INIT_SEQENCE
346 # define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
347 # define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
348 # define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */
349 # define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */
350 # define SDRAM_MPTRVALUE 0x400
351 #define SDRAM_MARVALUE 0x88
353 # define SDRAM_MxMR_PTx 128
354 # define UPM_MRS_ADDR 0x5
355 # define UPM_REFRESH_ADDR 0x30
356 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
358 static const uint sdram_table[] =
360 /* single read. (offset 0 in upm RAM) */
361 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
364 /* precharge + MRS. (offset 5 in upm RAM) */
365 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
367 /* burst read. (offset 8 in upm RAM) */
368 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
369 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
370 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
371 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
373 /* single write. (offset 18 in upm RAM) */
374 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
375 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
377 /* burst write. (offset 20 in upm RAM) */
378 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
379 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
380 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
381 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
383 /* refresh. (offset 30 in upm RAM) */
384 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
385 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
386 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
388 /* exception. (offset 3c in upm RAM) */
389 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
391 /* ------------------------------------------------------------------------- */
393 #error SDRAM not correctly configured
395 /* ------------------------------------------------------------------------- */
398 * Memory Periodic Timer Prescaler
401 #define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
402 #define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */
404 /* ------------------------------------------------------------------------- */
405 #ifdef SDRAM_ALT_INIT_SEQENCE
406 /* ------------------------------------------------------------------------- */
408 static int _initsdram(uint base, uint noMbytes)
410 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
411 volatile memctl8xx_t *memctl = &immap->im_memctl;
413 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
415 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
417 /* Configure the refresh (mostly). This needs to be
418 * based upon processor clock speed and optimized to provide
419 * the highest level of performance. For multiple banks,
420 * this time has to be divided by the number of banks.
421 * Although it is not clear anywhere, it appears the
422 * refresh steps through the chip selects for this UPM
423 * on each refresh cycle.
424 * We have to be careful changing
425 * UPM registers after we ask it to run these commands.
428 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
429 memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
433 /* Now run the precharge/nop/mrs commands.
436 memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
437 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
440 /* Run 8 refresh cycles */
442 memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/
443 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
447 memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */
448 memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */
449 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
453 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
455 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
456 memctl->memc_br4 = SDRAM_BR4VALUE | base;
461 /* ------------------------------------------------------------------------- */
462 #else /* !SDRAM_ALT_INIT_SEQUENCE */
463 /* ------------------------------------------------------------------------- */
465 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
466 # define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
467 # define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
469 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
470 # define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
471 # define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
474 * MxMR settings for SDRAM
478 # define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \
479 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
480 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
482 # define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \
483 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
484 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
486 static int _initsdram(uint base, uint noMbytes)
488 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
489 volatile memctl8xx_t *memctl = &immap->im_memctl;
491 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
493 memctl->memc_mptpr = MPTPR_2BK_4K;
494 memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
497 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
498 memctl->memc_br4 = SDRAM_BR4VALUE | base;
500 /* Perform SDRAM initilization */
501 # ifdef UPM_NOP_ADDR /* not currently in UPM table */
503 memctl->memc_mar = 0x00000000;
504 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
505 MCR_MLCF(0) | UPM_NOP_ADDR;
511 # ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
512 /* step 3: precharge */
513 memctl->memc_mar = 0x00000000;
514 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
515 MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
518 /* step 4: refresh */
519 memctl->memc_mar = 0x00000000;
520 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
521 MCR_MLCF(2) | UPM_REFRESH_ADDR;
524 * note: for some reason, the UPM values we are using include
529 memctl->memc_mar = 0x00000088;
530 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
531 MCR_MLCF(1) | UPM_MRS_ADDR;
534 memctl->memc_mar = 0x00000000;
535 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
536 MCR_MLCF(0) | UPM_NOP_ADDR;
542 memctl->memc_mbmr |= MBMR_PTBE;
545 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
547 /* ------------------------------------------------------------------------- */
549 static void _sdramdisable(void)
551 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
552 volatile memctl8xx_t *memctl = &immap->im_memctl;
554 memctl->memc_br4 = 0x00000000;
556 /* maybe we should turn off upmb here or something */
559 /* ------------------------------------------------------------------------- */
561 static int initsdram(uint base, uint *noMbytes)
563 uint m = CONFIG_SYS_SDRAM_SIZE>>20;
565 /* _initsdram needs access to sdram */
566 *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
568 if(!_initsdram(base, m))
575 *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
583 #endif /* CONFIG_FADS */
585 /* ========================================================================= */
587 phys_size_t initdram (int board_type)
589 uint sdramsz = 0; /* size of sdram in Mbytes */
590 uint m = 0; /* size of dram in Mbytes */
591 #ifndef CONFIG_MPC885ADS
592 uint base = 0; /* base of dram in bytes */
597 if (!initsdram (0x00000000, &sdramsz)) {
598 #ifndef CONFIG_MPC885ADS
599 base = sdramsz << 20;
601 printf ("(%u MB SDRAM) ", sdramsz);
604 #ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
605 k = (*((uint *) BCSR2) >> 23) & 0x0f;
608 /* "MCM36100 / MT8D132X" */
613 /* "MCM36800 / MT16D832X" */
617 /* "MCM36400 / MT8D432X" */
621 /* "MCM36200 / MT16D832X ?" */
638 printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
643 /* the FADS is missing this bit, all rams treated as non-edo */
646 s = (*((uint *) BCSR2) >> 27) & 0x01;
649 if (!_draminit (base, m, s, k)) {
650 printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
655 #endif /* !CONFIG_MPC885ADS */
656 m += sdramsz; /* add sdram size to total */
661 /* ------------------------------------------------------------------------- */
665 /* TODO: XXX XXX XXX */
666 printf ("test: 16 MB - ok\n");
671 /* ========================================================================= */
674 * Check Board Identity:
677 #if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD)
678 static void checkdboard(void)
680 /* get db type from BCSR 3 */
681 uint k = (*((uint *)BCSR3) >> 24) & 0x3f;
696 puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
708 default : printf("0x%x", k);
711 #endif /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */
713 int checkboard (void)
715 #if defined(CONFIG_MPC86xADS)
716 puts ("Board: MPC86xADS\n");
717 #elif defined(CONFIG_MPC885ADS)
718 puts ("Board: MPC885ADS\n");
719 #else /* Only old ADS/FADS have got revision ID in BCSR3 */
720 uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
721 | (((*((uint *) BCSR3) >> 19) & 1) << 2)
722 | (((*((uint *) BCSR3) >> 16) & 3));
725 #if defined(CONFIG_FADS)
735 #if defined(CONFIG_ADS)
737 puts ("ENG - this board sucks, check the errata, not supported\n");
740 puts ("PILOT - warning, read errata \n");
743 puts ("A - warning, read errata \n");
755 #endif /* CONFIG_ADS */
757 printf ("unknown (0x%x)\n", r);
760 #endif /* CONFIG_MPC86xADS */
765 /* ========================================================================= */
767 #if defined(CONFIG_CMD_PCMCIA)
769 #ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
770 volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
773 int pcmcia_init(void)
775 volatile pcmconf8xx_t *pcmp;
776 uint v, slota = 0, slotb = 0;
779 ** Enable the PCMCIA for a Flash card.
781 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
784 pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
785 pcmp->pcmc_por0 = 0xc00ff05d;
788 /* Set all slots to zero by default. */
789 pcmp->pcmc_pgcra = 0;
790 pcmp->pcmc_pgcrb = 0;
791 #ifdef CONFIG_PCMCIA_SLOT_A
792 pcmp->pcmc_pgcra = 0x40;
794 #ifdef CONFIG_PCMCIA_SLOT_B
795 pcmp->pcmc_pgcrb = 0x40;
798 /* enable PCMCIA buffers */
799 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
801 /* Check if any PCMCIA card is plugged in. */
803 #ifdef CONFIG_PCMCIA_SLOT_A
804 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
806 #ifdef CONFIG_PCMCIA_SLOT_B
807 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
810 if (!(slota || slotb)) {
811 printf("No card present\n");
812 pcmp->pcmc_pgcra = 0;
813 pcmp->pcmc_pgcrb = 0;
817 printf("Card present (");
821 /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
823 ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
827 #if defined(CONFIG_MPC86x)
828 switch ((pcmp->pcmc_pipr >> 30) & 3)
829 #elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
830 switch ((pcmp->pcmc_pipr >> 14) & 3)
840 v = 3; /* User lower voltage if supported! */
846 printf("5V, 3V and x.xV");
848 v = 3; /* User lower voltage if supported! */
858 printf("; using 3V");
860 ** Enable 3 volt Vcc.
862 *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
863 *((uint *)BCSR1) |= BCSR1_PCCVCC0;
867 printf("; using 5V");
870 ** Enable 5 volt Vcc.
872 *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
876 ** Enable 5 volt Vcc.
878 *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
879 *((uint *)BCSR1) |= BCSR1_PCCVCC1;
884 *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
886 printf("; unknown voltage");
890 /* disable pcmcia reset after a while */
894 #ifdef CONFIG_PCMCIA_SLOT_A
895 pcmp->pcmc_pgcra = 0;
897 #ifdef CONFIG_PCMCIA_SLOT_B
898 pcmp->pcmc_pgcrb = 0;
901 /* If you using a real hd you should give a short
903 #ifdef CONFIG_DISK_SPINUP_TIME
904 udelay(CONFIG_DISK_SPINUP_TIME);
912 /* ========================================================================= */
914 #ifdef CONFIG_SYS_PC_IDE_RESET
916 void ide_set_reset(int on)
918 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
921 * Configure PC for IDE Reset Pin
923 if (on) { /* assert RESET */
924 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
925 } else { /* release RESET */
926 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
929 /* program port pin as GPIO output */
930 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
931 immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
932 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
935 #endif /* CONFIG_SYS_PC_IDE_RESET */