1 /*----------------------------------------------------------------------+
2 * This source code is dual-licensed. You may use it under the terms of
3 * the GNU General Public License version 2, or under the license below.
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *-----------------------------------------------------------------------
29 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30 #define FPGA_BRDC 0xF0300004
32 #include <ppc_asm.tmpl>
35 #include <asm/cache.h>
40 /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
41 /* c-code declarations and consequently can't be included here). */
42 /* (Possibly to be solved somehow else). */
43 /*--------------------------------------------------------------------- */
44 #define I2C_REGISTERS_BASE_ADDRESS 0xEF600500
45 #define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
46 #define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
47 #define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
48 #define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
49 #define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
50 #define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
51 #define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
52 #define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
53 #define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
54 #define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
55 #define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
56 #define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
57 #define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
58 #define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
59 #define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
61 /* MDCNTL Register Bit definition */
62 #define IIC_MDCNTL_HSCL 0x01
63 #define IIC_MDCNTL_EUBS 0x02
64 #define IIC_MDCNTL_FMDB 0x40
65 #define IIC_MDCNTL_FSDB 0x80
67 /* CNTL Register Bit definition */
68 #define IIC_CNTL_PT 0x01
69 #define IIC_CNTL_READ 0x02
70 #define IIC_CNTL_CHT 0x04
72 /* STS Register Bit definition */
73 #define IIC_STS_PT 0X01
74 #define IIC_STS_ERR 0X04
75 #define IIC_STS_MDBS 0X20
77 /* EXTSTS Register Bit definition */
78 #define IIC_EXTSTS_XFRA 0X01
79 #define IIC_EXTSTS_ICT 0X02
80 #define IIC_EXTSTS_LA 0X04
82 /* LED codes used for inditing progress and errors during read of DIMM SPD. */
83 /*--------------------------------------------------------------------- */
84 #define LED_SDRAM_CODE_1 0xef
85 #define LED_SDRAM_CODE_2 0xee
86 #define LED_SDRAM_CODE_3 0xed
87 #define LED_SDRAM_CODE_4 0xec
88 #define LED_SDRAM_CODE_5 0xeb
89 #define LED_SDRAM_CODE_6 0xea
90 #define LED_SDRAM_CODE_7 0xe9
91 #define LED_SDRAM_CODE_8 0xe8
92 #define LED_SDRAM_CODE_9 0xe7
93 #define LED_SDRAM_CODE_10 0xe6
94 #define LED_SDRAM_CODE_11 0xe5
95 #define LED_SDRAM_CODE_12 0xe4
96 #define LED_SDRAM_CODE_13 0xe3
97 #define LED_SDRAM_CODE_14 0xe2
98 #define LED_SDRAM_CODE_15 0xe1
99 #define LED_SDRAM_CODE_16 0xe0
102 #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
104 #define FLASH_8bit_AP 0x9B015480
105 #define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */
107 #define FLASH_32bit_AP 0x9B015480
108 #define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */
111 #define WDCR_EBC(reg,val) addi r4,0,reg;\
117 /*---------------------------------------------------------------------
118 * Function: ext_bus_cntlr_init
119 * Description: Initializes the External Bus Controller for the external
120 * peripherals. IMPORTANT: For pass1 this code must run from
121 * cache since you can not reliably change a peripheral banks
122 * timing register (pbxap) while running code from that bank.
123 * For ex., since we are running from ROM on bank 0, we can NOT
124 * execute the code that modifies bank 0 timings from ROM, so
125 * we run it from cache.
126 * Bank 0 - Boot flash
127 * Bank 1-4 - application flash
130 * Bank 7 - Heathrow chip
131 *---------------------------------------------------------------------
133 .globl ext_bus_cntlr_init
135 mflr r4 /* save link register */
138 mflr r3 /* get address of ..getAddr */
139 mtlr r4 /* restore link register */
140 addi r4,0,14 /* set ctr to 10; used to prefetch */
141 mtctr r4 /* 10 cache lines to fit this function */
142 /* in cache (gives us 8x10=80 instrctns) */
144 icbt r0,r3 /* prefetch cache line for addr in r3 */
145 addi r3,r3,32 /* move to next cache line */
146 bdnz ..ebcloop /* continue for 10 cache lines */
148 mflr r31 /* save link register */
150 /*-----------------------------------------------------------
151 * Delay to ensure all accesses to ROM are complete before changing
152 * bank 0 timings. 200usec should be enough.
153 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
154 *-----------------------------------------------------------
158 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
161 bdnz ..spinlp /* spin loop */
163 /*---------------------------------------------------------------
164 * Memory Bank 0 (Boot Flash) initialization
165 *---------------------------------------------------------------
167 WDCR_EBC(pb0ap, FLASH_32bit_AP)
168 WDCR_EBC(pb0cr, 0xffe38000)
169 /*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */
171 /*---------------------------------------------------------------
172 * Memory Bank 5 (CPLD) initialization
173 *---------------------------------------------------------------
175 WDCR_EBC(pb5ap, 0x01010040)
176 /*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
177 WDCR_EBC(pb5cr, 0x10038000)
179 /*--------------------------------------------------------------- */
180 /* Memory Bank 6 (not used) initialization */
181 /*--------------------------------------------------------------- */
182 WDCR_EBC(pb6cr, 0x00000000)
184 /* Read HW ID to determine whether old H2 board or new generic CPU board */
185 addis r3, 0, HW_ID_ADDR@h
186 ori r3, r3, HW_ID_ADDR@l
188 cmpi 0, r3, 1 /* if (HW_ID==1) */
189 beq setup_h2evalboard /* then jump */
190 cmpi 0, r3, 2 /* if (HW_ID==2) */
191 beq setup_genieboard /* then jump */
192 cmpi 0, r3, 3 /* if (HW_ID==3) */
193 beq setup_genieboard /* then jump */
196 /*--------------------------------------------------------------- */
197 /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
198 /*--------------------------------------------------------------- */
199 /* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */
200 /* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
201 WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */
203 /* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */
204 WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */
206 /*--------------------------------------------------------------- */
207 /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
208 /*--------------------------------------------------------------- */
209 WDCR_EBC(pb4ap, 0x01010000) /* */
210 WDCR_EBC(pb4cr, 0x1021c000) /* */
212 /*--------------------------------------------------------------- */
213 /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
214 /*--------------------------------------------------------------- */
215 WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */
216 WDCR_EBC(pb7cr, 0X4001A000)
222 /*--------------------------------------------------------------- */
223 /* Memory Bank 1 (Application Flash) initialization */
224 /*--------------------------------------------------------------- */
225 WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */
226 /*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
227 WDCR_EBC(pb1cr, 0x20058000)
229 /*--------------------------------------------------------------- */
230 /* Memory Bank 2 (Application Flash) initialization */
231 /*--------------------------------------------------------------- */
232 WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */
233 /*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */
234 WDCR_EBC(pb2cr, 0x20458000)
236 /*--------------------------------------------------------------- */
237 /* Memory Bank 3 (Application Flash) initialization */
238 /*--------------------------------------------------------------- */
239 WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */
240 /*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */
241 WDCR_EBC(pb3cr, 0x20858000)
243 /*--------------------------------------------------------------- */
244 /* Memory Bank 4 (Application Flash) initialization */
245 /*--------------------------------------------------------------- */
246 WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */
247 /*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */
248 WDCR_EBC(pb4cr, 0x20C58000)
250 /*--------------------------------------------------------------- */
251 /* Memory Bank 7 (Heathrow chip) initialization */
252 /*--------------------------------------------------------------- */
253 WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */
254 WDCR_EBC(pb7cr, 0X4001A000)
259 mtlr r31 /* restore lr */
260 nop /* pass2 DCR errata #8 */
263 /*--------------------------------------------------------------------- */
264 /* Function: sdram_init */
265 /* Description: Configures SDRAM memory banks. */
266 /*--------------------------------------------------------------------- */
270 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
275 /* output SDRAM code on LEDs */
276 addi r4, 0, LED_SDRAM_CODE_1
282 /* Read contents of spd */
283 /*--------------------- */
286 /*----------------------------------------------------------- */
289 /* Update SDRAM timing register */
292 /*----------------------------------------------------------- */
294 /* Read PLL feedback divider and calculate clock period of local bus in */
295 /* granularity of 10 ps. Save clock period in r30 */
296 /*-------------------------------------------------------------- */
301 addis r5, 0, TIMEBASE_10PS@h
302 ori r5, r5, TIMEBASE_10PS@l
307 bl find_casl /* Returns CASL in r3 */
309 /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
310 /* (trp read from byte 27 in granularity of 1 ns) */
311 /*------------------------------------------------ */
318 /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
319 /* (trcd read from byte 29 in granularity of 1 ns) */
320 /*--------------------------------------------------- */
327 /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
328 /* (tras read from byte 30 in granularity of 1 ns) */
329 /*--------------------------------------------------- */
336 /* Calc trc_clocks = trp_clocks + tras_clocks */
337 /*------------------------------------------- */
345 /* PTA = trp_clocks - 1 */
346 /*--------------------- */
353 /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
354 /*------------------------------------------------ */
368 /* RFTA = trc_clocks - 4 */
369 /*---------------------- */
376 /* RCD = trcd_clocks - 1 */
377 /*---------------------- */
382 /*----------------------------------------------------------- */
384 /*----------------------------------------------------------- */
389 /*----------------------------------------------------------- */
392 /* Update memory bank 0-3 configuration registers */
395 /*----------------------------------------------------------- */
397 /* Build contents of configuration register for bank 0 into r6 */
398 /*------------------------------------------------------------ */
399 bl find_mode /* returns addressing mode in r3 */
400 addi r29, r3, 0 /* save mode temporarily in r29 */
401 bl find_size_code /* returns size code in r3 */
402 addi r9, 0, 17 /* bit offset of size code in configuration register */
404 addi r9, 0, 13 /* bit offset of addressing mode in configuration register */
405 slw r29, r29, r9 /* */
406 or r3, r29, r3 /* merge size code and addressing mode */
407 ori r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */
409 /* Calculate banksize r15 = (density << 22) / 2 */
410 /*--------------------------------------------- */
414 /* Set SDRAM bank 0 register and adjust r6 for next bank */
415 /*------------------------------------------------------ */
420 add r6, r6, r15 /* add bank size to base address for next bank */
422 /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
423 /*---------------------------------------------------------------------------- */
431 add r6, r6, r15 /* add bank size to base address for next bank */
433 /* Set SDRAM bank 2 register and adjust r6 for next bank */
434 /*------------------------------------------------------ */
435 b1skip: addi r7,0,mem_mb2cf
439 add r6, r6, r15 /* add bank size to base address for next bank */
441 /* If two rows/banks then set SDRAM bank 3 register */
442 /*------------------------------------------------ */
451 /*----------------------------------------------------------- */
453 /*----------------------------------------------------------- */
456 addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
458 rtr_1: addis r7, 0, 0x03F8
459 rtr_2: addi r4,0,mem_rtr
463 /*----------------------------------------------------------- */
464 /* Delay to ensure 200usec have elapsed since reset. Assume worst */
465 /* case that the core is running 200Mhz: */
466 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
467 /*----------------------------------------------------------- */
469 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
472 bdnz ..spinlp2 /* spin loop */
474 /*----------------------------------------------------------- */
475 /* Set memory controller options reg, MCOPT1. */
476 /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
478 /*----------------------------------------------------------- */
481 addis r4,0,0x80C0 /* set DC_EN=1 */
486 /*----------------------------------------------------------- */
487 /* Delay to ensure 10msec have elapsed since reset. This is */
488 /* required for the MPC952 to stabalize. Assume worst */
489 /* case that the core is running 200Mhz: */
490 /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
491 /* This delay should occur before accessing SDRAM. */
492 /*----------------------------------------------------------- */
494 ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
497 bdnz ..spinlp3 /* spin loop */
499 /* output SDRAM code on LEDs */
500 addi r4, 0, LED_SDRAM_CODE_16
506 mtlr r31 /* restore lr */
509 /*--------------------------------------------------------------------- */
510 /* Function: read_spd */
511 /* Description: Reads contents of SPD and saves parameters to be used for */
512 /* configuration in dedicated registers (see code below). */
513 /*--------------------------------------------------------------------- */
515 #define WRITE_I2C(reg,val) \
517 addis r4, 0, 0xef60;\
518 ori r4, r4, 0x0500 + reg;\
522 #define READ_I2C(reg) \
523 addis r3, 0, 0xef60;\
524 ori r3, r3, 0x0500 + reg;\
534 WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */
535 WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */
536 WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */
537 WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */
538 WRITE_I2C(IICSTS, 0x08) /* update status register */
539 WRITE_I2C(IICEXTSTS, 0x8f)
540 WRITE_I2C(IICCLKDIV, 0x05)
541 WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */
542 WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */
543 WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */
544 WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */
546 ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
547 WRITE_I2C(IICMDCNTL, r3) /* mode control */
548 WRITE_I2C(IICCNTL, 0x00) /* clear control reg */
550 /* Wait until initialization completed */
551 /*------------------------------------ */
552 bl wait_i2c_transfer_done
554 WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */
555 WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
557 /* Write 0 into buffer(start address) */
558 /*----------------------------------- */
559 WRITE_I2C(IICMDBUF, 0x00);
568 /* Issue write command */
569 /*-------------------- */
570 WRITE_I2C(IICCNTL, IIC_CNTL_PT)
571 bl wait_i2c_transfer_done
575 addi r7, 0, 0 /* byte counter in r7 */
576 addi r8, 0, 0 /* checksum in r8 */
578 /* issue read command */
579 /*------------------- */
582 WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
584 rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
585 rd02: bl wait_i2c_transfer_done
587 /* Fetch byte from buffer */
588 /*----------------------- */
591 /* Retrieve parameters that are going to be used during configuration. */
592 /* Save them in dedicated registers. */
593 /*------------------------------------------------------------ */
594 cmpi 0, r7, 3 /* Save byte 3 in r10 */
597 rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */
600 rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */
603 rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */
606 rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */
609 rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */
612 rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */
615 rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */
618 rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */
621 rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */
624 rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */
627 rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */
632 /* Calculate checksum of the first 63 bytes */
633 /*----------------------------------------- */
640 /* Verify checksum at byte 63 */
641 /*--------------------------- */
642 rd30: andi. r8, r8, 0xff /* use only 8 bits */
645 addi r4, 0, LED_SDRAM_CODE_8
654 /* Increment byte counter and check whether all bytes have been read. */
655 /*------------------------------------------------------------------- */
661 mtlr r5 /* restore lr */
664 wait_i2c_transfer_done:
666 wt01: READ_I2C(IICSTS)
667 andi. r4, r3, IIC_STS_PT
668 cmpi 0, r4, IIC_STS_PT
670 mtlr r6 /* restore lr */
673 /*--------------------------------------------------------------------- */
674 /* Function: find_mode */
675 /* Description: Determines addressing mode to be used dependent on */
676 /* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
677 /* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
678 /* mode is returned in r3. */
679 /* (It would be nicer having a table, pnc). */
680 /*--------------------------------------------------------------------- */
694 fm01: cmpi 0, r10, 11
703 fm02: cmpi 0, r10, 12
712 fm03: cmpi 0, r10, 12
721 fm04: cmpi 0, r10, 13
730 fm05: cmpi 0, r10, 13
739 fm06: cmpi 0, r10, 13
748 fm07: cmpi 0, r10, 12
757 fm08: cmpi 0, r10, 12
766 fm09: cmpi 0, r10, 11
775 fm10: cmpi 0, r10, 11
784 fm11: cmpi 0, r10, 13
793 fm12: cmpi 0, r10, 13
802 fm13: cmpi 0, r10, 13
811 fm14: cmpi 0, r10, 13
821 /* not found, error code to be issued on LEDs */
822 addi r7, 0, LED_SDRAM_CODE_2
829 fmfound:addi r6, 0, 1
832 mtlr r5 /* restore lr */
835 /*--------------------------------------------------------------------- */
836 /* Function: find_size_code */
837 /* Description: Determines size code to be used in configuring SDRAM controller */
838 /* dependent on density (r15 = byte 31 from SPD) */
839 /*--------------------------------------------------------------------- */
844 addi r3, r15, 0 /* density */
846 fs01: andi. r6, r3, 0x01
857 /* not found, error code to be issued on LEDs */
858 fs02: addi r4, 0, LED_SDRAM_CODE_3
871 mtlr r5 /* restore lr */
874 /*--------------------------------------------------------------------- */
875 /* Function: find_casl */
876 /* Description: Determines CAS latency */
877 /*--------------------------------------------------------------------- */
882 andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */
883 addi r3, 0, 0xff /* preset determined CASL */
884 addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */
885 addi r2, 0, 0 /* Start finding highest CAS latency */
887 fc01: srw r6, r14, r4 /* */
888 andi. r6, r6, 0x01 /* */
889 cmpi 0, r6, 1 /* Check bit for current latency */
890 bne fc06 /* If not supported, go to next */
892 cmpi 0, r2, 2 /* Check if third-highest latency */
893 bge fc04 /* If so, go calculate with another format */
895 cmpi 0, r2, 0 /* Check if highest latency */
897 addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */
901 addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */
916 addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */
930 fc05: addi r2, r2, 1 /* next latency */
940 mtlr r5 /* restore lr */
945 /* Peripheral Bank 1 Access Parameters */
946 /* 0 BME = 1 ; burstmode enabled */
947 /* " 1:8" TWT=00110110 ;Transfer wait (details below) */
948 /* 1:5 FWT=00110 ; first wait = 6 cycles */
949 /* 6:8 BWT=110 ; burst wait = 6 cycles */
950 /* 9:11 000 ; reserved */
951 /* 12:13 CSN=00 ; chip select on timing = 0 */
952 /* 14:15 OEN=01 ; output enable */
953 /* 16:17 WBN=01 ; write byte enable on timing 1 cycle */
954 /* 18:19 WBF=01 ; write byte enable off timing 1 cycle */
955 /* 20:22 TH=010 ; transfer hold = 2 cycles */
956 /* 23 RE=0 ; ready enable = disabled */
957 /* 24 SOR=1 ; sample on ready = same PerClk */
958 /* 25 BEM=0 ; byte enable mode = only for write cycles */
959 /* 26 PEN=0 ; parity enable = disable */
960 /* 27:31 00000 ;reserved */
962 /* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
965 /* Code for BDI probe: */
967 /* WDCR 18 0x00000011 ;Select PB1AP */
968 /* WDCR 19 0x1b015480 ;PB1AP: Flash */
970 /* Peripheral Bank 0 Access Parameters */
971 /* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */
972 /* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */
973 /* 15:16 BU=11 ; bank usage = read/write */
974 /* 17:18 BW=00 ; bus width = 8-bit */
975 /* 19:31 ; reserved */
977 /* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
978 /* WDCR 18 0x00000001 ;Select PB1CR */
979 /* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
982 /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
983 /* WDCR_EBC(pb5ap, 0x01010040) */
984 /*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
985 /* WDCR_EBC(pb5cr, 0X10018000) */
988 /* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
989 /* Address : 0x10000000 */
991 /* Usage: read/write */
994 /* For Genie onboard fpga 32 bit interface */
995 /* 0 1 0 1 0 0 0 0 */
996 /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
1000 /* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
1001 /* Address : 0x10200000 */
1003 /* Usage: read/write */
1006 /* Walnut fpga pb7ap */
1007 /* 0 1 8 1 5 2 8 0 */
1008 /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
1009 /* Walnut fpga pb7cr */