3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* sdram_init.c - automatic memory sizing */
28 #include <galileo/memory.h>
29 #include <galileo/pci.h>
30 #include <galileo/gt64260R.h>
49 /* structure to store the relevant information about an sdram bank */
50 typedef struct sdram_info {
52 uchar registered, ecc;
57 int size; /* detected size, not from I2C but from dram_size() */
61 void dump_dimm_info (struct sdram_info *d)
63 static const char *ecc_legend[] = { "", " Parity", " ECC" };
65 printf ("dimm%s %sDRAM: %dMibytes:\n",
67 d->registered ? "R" : "", (d->size >> 20));
68 printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
69 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
75 memory_map_bank (unsigned int bankNo,
76 unsigned int bankBase, unsigned int bankLength)
80 printf ("mapping bank %d at %08x - %08x\n",
81 bankNo, bankBase, bankBase + bankLength - 1);
83 printf ("unmapping bank %d\n", bankNo);
87 memoryMapBank (bankNo, bankBase, bankLength);
94 memory_map_bank_pci (unsigned int bankNo,
95 unsigned int bankBase, unsigned int bankLength)
99 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
102 DELAYED_READ_ENABLE |
103 AGGRESSIVE_PREFETCH |
104 READ_LINE_AGGRESSIVE_PREFETCH |
105 READ_MULTI_AGGRESSIVE_PREFETCH |
106 MAX_BURST_4 | PCI_NO_SWAP;
108 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
110 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
113 pciSetRegionFeatures (host, bankNo, features, bankBase,
120 /* ------------------------------------------------------------------------- */
122 /* much of this code is based on (or is) the code in the pip405 port */
123 /* thanks go to the authors of said port - Josh */
127 * translate ns.ns/10 coding of SPD timing values
128 * into 10 ps unit values
130 static inline unsigned short NS10to10PS (unsigned char spd_byte)
132 unsigned short ns, ns10;
134 /* isolate upper nibble */
135 ns = (spd_byte >> 4) & 0x0F;
136 /* isolate lower nibble */
137 ns10 = (spd_byte & 0x0F);
139 return (ns * 100 + ns10 * 10);
143 * translate ns coding of SPD timing values
144 * into 10 ps unit values
146 static inline unsigned short NSto10PS (unsigned char spd_byte)
148 return (spd_byte * 100);
151 #ifdef CONFIG_ZUMA_V2
152 static int check_dimm (uchar slot, sdram_info_t * info)
154 /* assume 2 dimms, 2 banks each 256M - we dont have an
155 * dimm i2c so rely on the detection routines later */
157 memset (info, 0, sizeof (*info));
160 info->banks = 2; /* Detect later */
161 info->registered = 0;
162 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
163 but doesn't matter, both do same
164 thing in setup_sdram() */
166 info->tras_clocks = 5;
169 info->ecc = 0; /* Detect later */
170 #endif /* CONFIG_ECC */
174 #elif defined(CONFIG_P3G4)
176 static int check_dimm (uchar slot, sdram_info_t * info)
178 memset (info, 0, sizeof (*info));
185 info->registered = 0;
188 info->tras_clocks = 6;
196 #else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
198 /* This code reads the SPD chip on the sdram and populates
199 * the array which is passed in with the relevant information */
200 static int check_dimm (uchar slot, sdram_info_t * info)
202 DECLARE_GLOBAL_DATA_PTR;
203 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
205 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
207 uchar trp_clocks, trcd_clocks;
212 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
214 #ifdef CONFIG_EVB64260_750CX
216 printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
217 printf (" called with slot=%d insetad!\n", slot);
221 DP (puts ("before i2c read\n"));
223 ret = i2c_read (addr, 0, 128, data, 0);
225 DP (puts ("after i2c read\n"));
227 /* zero all the values */
228 memset (info, 0, sizeof (*info));
231 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
235 /* first, do some sanity checks */
236 if (data[2] != 0x4) {
237 printf ("Not SDRAM in slot %d\n", slot);
241 /* get various information */
244 info->banks = data[5];
245 sdram_banks = data[17];
246 width = data[13] & 0x7f;
249 ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
251 /* check if the memory is registered */
252 if (data[21] & (BIT1 | BIT4))
253 info->registered = 1;
256 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
257 info->ecc = (data[11] & 2) >> 1;
260 /* bit 1 is CL2, bit 2 is CL3 */
261 supp_cal = (data[18] & 0x6) >> 1;
263 /* compute the relevant clock values */
264 trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
265 trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
266 info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
268 DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
269 trp_clocks, trcd_clocks, info->tras_clocks));
271 /* try a CAS latency of 3 first... */
274 if (NS10to10PS (data[9]) <= tmemclk)
280 if (NS10to10PS (data[23]) <= tmemclk)
284 DP (printf ("cal_val = %d\n", cal_val));
286 /* bummer, did't work... */
288 DP (printf ("Couldn't find a good CAS latency\n"));
292 /* get the largest delay -- these values need to all be the same
294 info->tpar = cal_val;
295 if (trp_clocks > info->tpar)
296 info->tpar = trp_clocks;
297 if (trcd_clocks > info->tpar)
298 info->tpar = trcd_clocks;
300 DP (printf ("tpar set to: %d\n", info->tpar));
302 #ifdef CFG_BROKEN_CL2
303 if (info->tpar == 2) {
305 DP (printf ("tpar fixed-up to: %d\n", info->tpar));
308 /* compute the module DRB size */
310 (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
312 DP (printf ("drb_size set to: %d\n", info->drb_size));
314 /* find the burst len */
315 info->burst_len = data[16] & 0xf;
316 if ((info->burst_len & 8) == 8) {
318 } else if ((info->burst_len & 4) == 4) {
327 #endif /* ! CONFIG_ZUMA_V2 */
329 static int setup_sdram_common (sdram_info_t info[2])
332 int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
334 if (!info[0].banks && !info[1].banks)
338 if (info[0].tpar > tpar)
340 if (info[0].tras_clocks > tras_clocks)
341 tras_clocks = info[0].tras_clocks;
342 if (!info[0].registered)
344 if (info[0].ecc != 2)
349 if (info[1].tpar > tpar)
351 if (info[1].tras_clocks > tras_clocks)
352 tras_clocks = info[1].tras_clocks;
353 if (!info[1].registered)
355 if (info[1].ecc != 2)
359 /* SDRAM configuration */
360 tmp = GTREGREAD (SDRAM_CONFIGURATION);
362 /* Turn on physical interleave if both DIMMs
363 * have even numbers of banks. */
364 if ((info[0].banks == 0 || info[0].banks == 2) &&
365 (info[1].banks == 0 || info[1].banks == 2)) {
366 /* physical interleave on */
369 /* physical interleave off */
373 tmp |= (registered << 17);
375 /* Use buffer 1 to return read data to the CPU
379 GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
380 DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
383 tmp = (((tpar == 3) ? 2 : 1) |
384 (((tpar == 3) ? 2 : 1) << 2) |
385 (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
391 #endif /* CONFIG_ECC */
393 GT_REG_WRITE (SDRAM_TIMING, tmp);
394 DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
395 GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
397 /* SDRAM address decode register */
398 /* program this with the default value */
399 GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
400 DP (printf ("SDRAM decode: %08x\n",
401 GTREGREAD (SDRAM_ADDRESS_DECODE)));
406 /* sets up the GT properly with information passed in */
407 static int setup_sdram (sdram_info_t * info)
413 /* sanity checking */
417 /* ---------------------------- */
418 /* Program the GT with the discovered data */
420 /* bank parameters */
421 tmp = (0xf << 16); /* leave all virt bank pages open */
423 DP (printf ("drb_size: %d\n", info->drb_size));
424 switch (info->drb_size) {
437 printf ("Error in dram size calculation\n");
441 /* SDRAM bank parameters */
442 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
443 GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
444 GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
446 ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
447 info->slot * 2, (info->slot * 2) + 1, tmp));
449 /* set the SDRAM configuration for each bank */
450 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
451 DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
454 memory_map_bank (i, 0, GB / 4);
457 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
458 check = GTREGREAD (SDRAM_OPERATION_MODE);
463 /* wait for the command to complete */
464 while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
466 /* switch back to normal operation mode */
467 GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
468 check = GTREGREAD (SDRAM_OPERATION_MODE);
471 memory_map_bank (i, 0, 0);
472 DP (printf ("*** MRS cycle for bank %d done ***\n", i));
479 * Check memory range for valid RAM. A simple memory test determines
480 * the actually available RAM size between addresses `base' and
481 * `base + maxsize'. Some (not all) hardware errors are detected:
482 * - short between address lines
483 * - short between data lines
485 static long int dram_size (long int *base, long int maxsize)
487 volatile long int *addr, *b = base;
488 long int cnt, val, save1, save2;
490 #define STARTVAL (1<<20) /* start test at 1M */
491 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
493 addr = base + cnt; /* pointer arith! */
495 save1 = *addr; /* save contents of addr */
496 save2 = *b; /* save contents of base */
498 *addr = cnt; /* write cnt to addr */
499 *b = 0; /* put null at base */
501 /* check at base address */
503 *addr = save1; /* restore *addr */
504 *b = save2; /* restore *b */
507 val = *addr; /* read *addr */
513 /* fix boundary condition.. STARTVAL means zero */
514 if (cnt == STARTVAL / sizeof (long))
516 return (cnt * sizeof (long));
522 /* ------------------------------------------------------------------------- */
524 /* U-Boot interface function to SDRAM init - this is where all the
525 * controlling logic happens */
526 long int initdram (int board_type)
528 ulong checkbank[4] = {[0 ... 3] = 0 };
532 sdram_info_t dimm_info[2];
535 /* first, use the SPD to get info about the SDRAM */
537 /* check the NHR bit and skip mem init if it's already done */
538 nhr = get_hid0 () & (1 << 16);
541 printf ("Skipping SDRAM setup due to NHR bit being set\n");
544 check_dimm (0, &dimm_info[0]);
547 #ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
548 check_dimm (1, &dimm_info[1]);
549 #else /* CONFIG_EVB64260_750CX */
550 memset (&dimm_info[1], 0, sizeof (sdram_info_t));
553 /* unmap all banks */
554 memory_map_bank (0, 0, 0);
555 memory_map_bank (1, 0, 0);
556 memory_map_bank (2, 0, 0);
557 memory_map_bank (3, 0, 0);
559 /* Now, program the GT with the correct values */
560 if (setup_sdram_common (dimm_info)) {
561 printf ("Setup common failed.\n");
564 if (setup_sdram (&dimm_info[0])) {
565 printf ("Setup for DIMM1 failed.\n");
568 if (setup_sdram (&dimm_info[1])) {
569 printf ("Setup for DIMM2 failed.\n");
572 /* set the NHR bit */
573 set_hid0 (get_hid0 () | (1 << 16));
575 /* next, size the SDRAM banks */
578 if (dimm_info[0].banks > 0)
580 if (dimm_info[0].banks > 1)
582 if (dimm_info[0].banks > 2)
583 printf ("Error, SPD claims DIMM1 has >2 banks\n");
585 if (dimm_info[1].banks > 0)
587 if (dimm_info[1].banks > 1)
589 if (dimm_info[1].banks > 2)
590 printf ("Error, SPD claims DIMM2 has >2 banks\n");
592 /* Generic dram sizer: works even if we don't have i2c DIMMs,
593 * as long as the timing settings are more or less correct */
596 * pass 1: size all the banks, using first bat (0-256M)
597 * limitation: we only support 256M per bank due to
598 * us only having 1 BAT for all DRAM
600 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
601 /* skip over banks that are not populated */
602 if (!checkbank[bank_no])
605 DP (printf ("checking bank %d\n", bank_no));
607 memory_map_bank (bank_no, 0, GB / 4);
608 checkbank[bank_no] = dram_size (NULL, GB / 4);
609 memory_map_bank (bank_no, 0, 0);
611 DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
615 * pass 2: contiguously map each bank into physical address
618 dimm_info[0].banks = dimm_info[1].banks = 0;
619 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
620 if (!checkbank[bank_no])
623 dimm_info[bank_no / 2].banks++;
624 dimm_info[bank_no / 2].size += checkbank[bank_no];
626 memory_map_bank (bank_no, total, checkbank[bank_no]);
628 memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
630 total += checkbank[bank_no];
634 #ifdef CONFIG_ZUMA_V2
636 * We always enable ECC when bank 2 and 3 are unpopulated
637 * If we 2 or 3 are populated, we CAN'T support ECC.
638 * (Zuma boards only support ECC in banks 0 and 1; assume that
639 * in that configuration, ECC chips are mounted, even for stacked
642 if (checkbank[2] == 0 && checkbank[3] == 0) {
643 dimm_info[0].ecc = 2;
644 GT_REG_WRITE (SDRAM_TIMING,
645 GTREGREAD (SDRAM_TIMING) | (1 << 13));
646 /* TODO: do we have to run MRS cycles again? */
648 #endif /* CONFIG_ZUMA_V2 */
650 if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
653 #endif /* CONFIG_ECC */
656 dump_dimm_info (&dimm_info[0]);
657 dump_dimm_info (&dimm_info[1]);
659 /* TODO: return at MOST 256M? */
660 /* return total > GB/4 ? GB/4 : total; */