3 * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 DECLARE_GLOBAL_DATA_PTR;
35 /*TODO: Check processor type */
37 puts ( "Board: Debris "
44 " ##Test not implemented yet##\n");
51 /* TODO: XXX XXX XXX */
52 printf ("## Test not implemented yet ##\n");
58 phys_size_t initdram (int board_type)
60 int m, row, col, bank, i;
61 unsigned long start, end;
63 uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
64 uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
67 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
69 if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
70 m = i2c_reg_read (0x50, 5); /* # of physical banks */
71 row = i2c_reg_read (0x50, 3); /* # of rows */
72 col = i2c_reg_read (0x50, 4); /* # of columns */
73 bank = i2c_reg_read (0x50, 17); /* # of logical banks */
75 CONFIG_READ_WORD(MCCR1, mccr1);
78 start = CONFIG_SYS_SDRAM_BASE;
79 end = start + (1 << (col + row + 3) ) * bank - 1;
81 for (i = 0; i < m; i++) {
82 mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
84 msar1 |= ((start >> 20) & 0xff) << i * 8;
85 emsar1 |= ((start >> 28) & 0xff) << i * 8;
86 mear1 |= ((end >> 20) & 0xff) << i * 8;
87 emear1 |= ((end >> 28) & 0xff) << i * 8;
89 msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
90 emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
91 mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
92 emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
95 start += (1 << (col + row + 3) ) * bank;
96 end += (1 << (col + row + 3) ) * bank;
100 msar1 |= 0xff << i * 8;
101 emsar1 |= 0x30 << i * 8;
102 mear1 |= 0xff << i * 8;
103 emear1 |= 0x30 << i * 8;
105 msar2 |= 0xff << (i-4) * 8;
106 emsar2 |= 0x30 << (i-4) * 8;
107 mear2 |= 0xff << (i-4) * 8;
108 emear2 |= 0x30 << (i-4) * 8;
112 CONFIG_WRITE_WORD(MCCR1, mccr1);
113 CONFIG_WRITE_WORD(MSAR1, msar1);
114 CONFIG_WRITE_WORD(EMSAR1, emsar1);
115 CONFIG_WRITE_WORD(MEAR1, mear1);
116 CONFIG_WRITE_WORD(EMEAR1, emear1);
117 CONFIG_WRITE_WORD(MSAR2, msar2);
118 CONFIG_WRITE_WORD(EMSAR2, emsar2);
119 CONFIG_WRITE_WORD(MEAR2, mear2);
120 CONFIG_WRITE_WORD(EMEAR2, emear2);
121 CONFIG_WRITE_BYTE(MBER, mber);
123 return (1 << (col + row + 3) ) * bank * m;
127 * Initialize PCI Devices, report devices found.
129 #ifndef CONFIG_PCI_PNP
130 static struct pci_config_table pci_debris_config_table[] = {
131 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
132 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
134 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
135 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
136 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
138 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
143 struct pci_controller hose = {
144 #ifndef CONFIG_PCI_PNP
145 config_table: pci_debris_config_table,
149 void pci_init_board(void)
151 pci_mpc824x_init(&hose);
154 void *nvram_read(void *dest, const long src, size_t count)
156 volatile uchar *d = (volatile uchar*) dest;
157 volatile uchar *s = (volatile uchar*) src;
160 asm volatile("sync");
165 void nvram_write(long dest, const void *src, size_t count)
167 volatile uchar *d = (volatile uchar*)dest;
168 volatile uchar *s = (volatile uchar*)src;
171 asm volatile("sync");
175 int misc_init_r(void)
179 if (eth_getenv_enetaddr("ethaddr", ethaddr))
180 /* Write ethernet addr in NVRAM for VxWorks */
181 nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
187 int board_eth_init(bd_t *bis)
189 return pci_eth_init(bis);